Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one trim layer and at least one masking layer under the trim layer. The trim layer may have structures that have smaller linewidths than the structures of the patterned layer by utilizing an isotropic gaseous process to trim the structures of the trim layer. The structures of the trim layer, after trimming, may then be replicated in the mask layer to provide a linewidth in the mask layer that is smaller than the linewidth in the patterned layer. The technique may allow nanometer control of an EUV lithography process at pitches of 36 nm or less. In one embodiment, the technique may be utilized to provide an EUV lithography process for increasing the trench dimensions in a BEOL trench formation process step.

Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures spaced apart from each other on a fin, forming an inorganic plug portion on the fin between at least two gate structures of the plurality of gate structures, forming a dielectric layer on the fin and between remaining gate structures of the plurality of gate structures, forming an organic planarizing layer (OPL) on the plurality of gate structures and on the inorganic plug portion, removing a portion of the OPL to expose the inorganic plug portion, selectively removing the inorganic plug portion, and forming a contact on the fin in place of the removed inorganic plug portion.

Abstract: Semiconductor devices and methods of forming the same include forming dummy gates over a semiconductor fin. An interlayer dielectric is formed around and between the dummy gates. The dummy gates are etched away, leaving gate voids. A first planarizing material is deposited in and over the gate voids. The first planarizing material is removed in a gate cut region. A gate cut plug is deposited in the gate cut region. The remaining first planarizing material is removed to expose the gate voids outside of the gate cut region. A gate stack is formed in the gate voids outside of the gate cut region.

Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one trim layer and at least one masking layer under the trim layer. The trim layer may have structures that have smaller linewidths than the structures of the patterned layer by utilizing an isotropic gaseous process to trim the structures of the trim layer. The structures of the trim layer, after trimming, may then be replicated in the mask layer to provide a linewidth in the mask layer that is smaller than the linewidth in the patterned layer. The technique may allow nanometer control of an EUV lithography process at pitches of 36 nm or less. In one embodiment, the technique may be utilized to provide an EUV lithography process for increasing the trench dimensions in a BEOL trench formation process step.

Abstract: A security system for disconnected automation devices comprises a central access control authority that provides access regulations that are received by a portable unit. An analysis component that determines whether access should be provided to a disconnected system based at least in part upon the access regulations. In accordance with an aspect of the present invention, for example, the access regulations can restrict access to a disconnected device for a particular timeframe.

Abstract: Various embodiments are described in connection with auto-detection capabilities of a device in an industrial environment. The device can behave differently in a secured environment than it would in an unsecured environment. If in a secured environment, the device can obtain an auto configuration policy to control the device's security configuration from a security authority, for example. The device can configure itself based on the policy. Both secured-by-default and open-by-default can be supported based on the environment. According to some embodiments, needed security domain specific knowledge can be reduced, which increases the number of maintenance personnel that can add or replace a device in a secured system.

Abstract: An industrial controller for injection molding machines models the injection molding machine by observing ram state in response to control variables to alert the user when a control profile may be physically unrealizable and to inhibit a learning process to avoid extreme actuation of the controlled components such as may be detrimental to later control accuracy. Simultaneous velocity and pressure control of the ram, with separate profiles, may be obtained by open-loop control of either pressure or velocity and continuous closed-loop control of the other control variable.