Patents by Inventor Jeffrey A. Tindle

Jeffrey A. Tindle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240110954
    Abstract: An electromagnetic pulse detector in an integrated circuit includes one or more peak hold circuits coupled to one or more traces in the integrated circuit and configured to asynchronously detect voltage spike(s) on the one or more traces and store voltage value(s) corresponding to the voltage spike(s). One or more comparator circuits are coupled to the peak hold circuits to compare the voltage values corresponding to the voltage spikes to one or more threshold voltage values. Storage locations are coupled to the comparator circuits to store indications of the voltage spike(s) being greater than the threshold voltage value to thereby indicate detection of an electromagnetic pulse.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: DeWitt C. Seward, Attila Zolomy, Clayton Daigle, Jeffrey Tindle
  • Publication number: 20230420869
    Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Attila Zólomy, Ádám Süle, Joel Kauppo, Terry Lee Dickey, Jeffrey Tindle
  • Patent number: 11611152
    Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: March 21, 2023
    Assignee: Silicon Laboratories
    Inventors: Attila Zólomy, Adám Süle, Andrea Nagy, Jeffrey Tindle, Pasi Rahikkala, Terry Lee Dickey
  • Publication number: 20220416439
    Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. A ground skirt surrounds the perimeter of the antenna array to improve radiation phase pattern balance within the array.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 29, 2022
    Inventors: Attila Zólomy, Ádám Süle, Daniel Simon, Kiruba Sankaran Subramani, Terry Lee Dickey, Jeffrey Tindle
  • Publication number: 20220416436
    Abstract: An antenna array that utilizes ground guard rings and metamaterial structures is disclosed. In certain embodiments, the antenna array is constructed from a plurality of antenna unit cells, wherein each antenna unit cell is identical. The antenna unit cell comprises a top surface, that contains a patch antenna and a ground guard ring. A reactive impedance surface (RIS) layer is disposed beneath the top surface and contains the metamaterial structures. The metamaterial structures are configured to present an inductance to the patch antennas, thereby allowing the patch antennas to be smaller than would otherwise be possible. In some embodiments, the metamaterial structures comprise hollow square frames. An antenna array constructed using this antenna unit cell has less coupling than conventional antenna arrays, which results in better performance. Furthermore, this new antenna array also requires less space than conventional antenna arrays.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Attila Zólomy, Adám Süle, Andrea Nagy, Jeffrey Tindle, Pasi Rahikkala, Terry Lee Dickey
  • Publication number: 20220399869
    Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
    Type: Application
    Filed: August 22, 2022
    Publication date: December 15, 2022
    Inventors: Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Patent number: 11463064
    Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: October 4, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Patent number: 11387857
    Abstract: A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: July 12, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Arup Mukherji, Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Publication number: 20220085787
    Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Publication number: 20210175870
    Abstract: A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Publication number: 20210175917
    Abstract: A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.
    Type: Application
    Filed: August 20, 2020
    Publication date: June 10, 2021
    Inventors: Arup Mukherji, Vitor Pereira, Jeffrey A. Tindle, Mustafa H. Koroglu, Terry Lee Dickey
  • Patent number: 10763781
    Abstract: A system and method of performing temperature compensation based on temperature of a crystal. An integrated circuit includes a clock circuit, a memory, an interface developing a sense voltage indicative of a temperature of the crystal, and a controller. The memory stores compensation values including nominal values based on a nominal third order polynomial that defines a nominal frequency versus temperature relationship of a crystal design representing multiple crystals, and a pair of adjustment values derived from two temperature-frequency error points. The controller determines a temperature value based on the sense voltage, calculates a frequency offset using the temperature value and the compensation values to solve a compensated third order polynomial defining a compensated frequency versus temperature relationship of the crystal, and adjusts a clock signal of the clock circuit using the frequency offset. A Wi-Fi device may be optimized for industrial IoT operating within an extended temperature range.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 1, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Thomas Edward Voor, Jeffrey A. Tindle, Euisoo Yoo, Wei Shen
  • Publication number: 20190305725
    Abstract: A system and method of performing temperature compensation based on temperature of a crystal. An integrated circuit includes a clock circuit, a memory, an interface developing a sense voltage indicative of a temperature of the crystal, and a controller. The memory stores compensation values including nominal values based on a nominal third order polynomial that defines a nominal frequency versus temperature relationship of a crystal design representing multiple crystals, and a pair of adjustment values derived from two temperature-frequency error points. The controller determines a temperature value based on the sense voltage, calculates a frequency offset using the temperature value and the compensation values to solve a compensated third order polynomial defining a compensated frequency versus temperature relationship of the crystal, and adjusts a clock signal of the clock circuit using the frequency offset. A Wi-Fi device may be optimized for industrial IoT operating within an extended temperature range.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 3, 2019
    Inventors: THOMAS EDWARD VOOR, JEFFREY A. TINDLE, EUISOO YOO, WEI SHEN
  • Patent number: 9252891
    Abstract: Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that the operation of receive path circuitry can be adjusted without requiring intervention from an external host processor integrated circuit. A variety of operating parameter information can be communicated through the die-to-die communication links so that the integrated circuit dies can quickly adjust to changing signal conditions without requiring intervention by the external host processor integrated circuit.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: February 2, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: John B. Youngblood, Guner Arslan, J. A. Bolton, Trenton J. Grale, Vitor Pereira, Jeffrey A. Tindle, David S. Trager, Yan Zhou
  • Publication number: 20150126128
    Abstract: Die-to-die communication links for receiver integrated circuit dies within multi-die systems and related methods are disclosed for radio frequency (RF) receivers. The disclosed embodiments provide die-to-die communication links that allow for direct communication of operating parameters between receiver integrated circuit dies and other integrated circuit dies within a multi-die system so that the operation of receive path circuitry can be adjusted without requiring intervention from an external host processor integrated circuit. A variety of operating parameter information can be communicated through the die-to-die communication links so that the integrated circuit dies can quickly adjust to changing signal conditions without requiring intervention by the external host processor integrated circuit.
    Type: Application
    Filed: December 18, 2014
    Publication date: May 7, 2015
    Inventors: John B. Youngblood, Guner Arslan, J.A. Bolton, Trenton J. Grale, Vitor Pereira, Jeffrey A. Tindle, David S. Trager, Yan Zhou