Abstract: One embodiment of a power supply apparatus includes a first switcher coupled to provide VOUT from a VSUPPLY. A cascaded second switcher is coupled to provide a subscriber line interface circuit target VBAT from VOUT, wherein the first switcher is placed in one of an active mode and an inactive mode in accordance with a function of VSUPPLY and VBAT, wherein in the active mode ? VOUT VSUPPLY ? ? 1 , wherein in the inactive mode VOUT?VSUPPLY.

Abstract: In one embodiment, a subscriber line interface circuit includes circuitry to generate metering pulses for insertion onto a subscriber line. The circuitry includes an audio path and a pulse metering path, where the pulse metering path includes a metering generator to generate a digital sine wave from a plurality of stored values, a first interpolator to interpolate the digital sine wave, a filter to filter the interpolated digital sine wave, and a second interpolator to interpolate the filtered interpolated digital sine wave.

Abstract: Methods and apparatus for communicating include communicating frames of data having a first timeslot allocation of s timeslots serially from a first device to a second device using a first unidirectional data line at a frequency f1. An edge of each frame as a detected edge. A clock signal having a frequency f2 is generated in response to the detected edges, wherein f 2 f 1 ? n · s , wherein n>1, wherein the clock signal is maintained substantially synchronous to the detected edges. Frames of data having a second timeslot allocation of s timeslots are communicated serially from the second device to the first device using a second unidirectional data line at the frequency f1 as derived from f2.

Abstract: Methods and apparatus for synchronizing communications between a first and a second device include serially communicating a frame having a first format from a first device to a second device, wherein only a frame synchronization timeslot (F1) is asserted. The serially communicated frame having the first format is sampled by the second device until the asserted F1 timeslot is detected. The second device serially communicates a frame having a second format to the first device, wherein only a frame synchronization timeslot (R1) is asserted. The serially communicated frame having the second format is sampled by the first device until the asserted R1 timeslot is detected. The first device establishes synchronization when these steps are successfully repeated. On the second sampling to detect the F1 timeslot, however, the sampling is windowed to less than one timeslot within the expected occurrence of the F1 timeslot.

Abstract: Methods and apparatus for communicating include a first device coupled to a second device with a bi-directional data line and a clock line. Frames of data are serially communicated between the first and second devices on the data line. Each frame is synchronized with a clock signal carried by the clock line. Each frame has a portion allocated to data communicated from the first device to the second device and another portion allocated to data communicated from the second device to the first device.

Abstract: Methods and apparatus for communicating include communicating frames of data at a frequency f1 serially from a first device to a second device using a first unidirectional data line. The frames have a first timeslot allocation of s timeslots. A clock signal having a frequency f2 is generated within the second device, wherein f 2 f 1 ? n · s , wherein n>1. The first unidirectional data line is sampled every n clock cycles of the clock signal for a plurality of the timeslots.

Abstract: Methods and apparatus for communicating include coupling first and second devices with a first unidirectional data line, a second unidirectional data line, and a clock line. Frames of data are serially communicated between the first and second devices using the first and second unidirectional data lines. The frame format of a frame carried by the first unidirectional data line is distinct from a frame format of a frame carried by the second unidirectional data line. Each frame is synchronized with a clock signal carried by the clock line.

Abstract: One embodiment of a power supply apparatus includes a switching regulator generating an output voltage VOUT at an output node from an input voltage VIN at an input node in accordance with a pulse width modulated signal having a nominal frequency of fs. A pulse width modulator provides the pulse width modulated signal in accordance with a pulse control signal. A digital control loop sampling the second voltage to provide an m-bit sampled value at a sampling rate, f1. The digital control loop includes a loop filter providing a filtered value from the sampled value and a delta sigma modulator sampling the filtered value as an n-bit value at a frequency f2 to provide the pulse control signal, wherein m>n.

Abstract: One embodiment of a power supply apparatus includes a first switcher coupled to provide VOUT from a VSUPPLY. A cascaded second switcher is coupled to provide a subscriber line interface circuit target VBAT from VOUT, wherein the first switcher is placed in one of an active mode and an inactive mode in accordance with a function of VSUPPLY and VBAT, wherein in the active mode ? VOUT VSUPPLY ? ? 1 , wherein in the inactive mode VOUT?VSUPPLY.

Abstract: An apparatus for offloading power includes a power offload element providing a supply drop from a first supply level to a second supply level. The supply drop varies in response to a control signal. A signal processor of a subscriber line interface circuit provides the control signal. A linefeed driver of the subscriber line interface circuit is coupled to receive the second supply level for driving a subscriber line.

Abstract: In one embodiment, a subscriber line interface circuit includes circuitry to generate metering pulses for insertion onto a subscriber line. The circuitry includes a cascaded digital-to-analog converter (DAC) structure including a first DAC to convert a digital sine wave into an analog representation, a second DAC to multiply the analog representation with a ramp value to obtain an unscaled output, and a third DAC to multiply the unscaled output with a gain value to generate a metering pulse.

Abstract: In one embodiment, a subscriber line interface circuit includes circuitry to generate metering pulses for insertion onto a subscriber line. The circuitry includes an audio path and a pulse metering path, where the pulse metering path includes a metering generator to generate a digital sine wave from a plurality of stored values, a first interpolator to interpolate the digital sine wave, a filter to filter the interpolated digital sine wave, and a second interpolator to interpolate the filtered interpolated digital sine wave.

Abstract: In one embodiment, a subscriber line interface circuit includes circuitry to generate metering pulses for insertion onto a subscriber line. The circuitry includes a cascaded digital-to-analog converter (DAC) structure including a first DAC to convert a digital sine wave into an analog representation, a second DAC to multiply the analog representation with a ramp value to obtain an unscaled output, and a third DAC to multiply the unscaled output with a gain value to generate a metering pulse.

Abstract: An integrated circuit maintains status information for a communications channel. The integrated circuit selects a portion of the status information maintained for the communications channel. The integrated circuit repeatedly transmits the selected portion of status information over a time-division multiplexed channel to a host.