Abstract: An integrated circuit (IC) device package includes an IC device connected to an upper surface of the IC device carrier. Due to operation conditions or IC device package makeup, the IC device may warp. The warped IC device may include a convex upper surface. A conformable lid is connected to the IC device and includes an internal chamber and a deformable floor. The deformable floor is able to deform or bend along with the IC device. After deformation, the deformable floor may include a concave lower surface. A uniform bond line thickness of a thermal interface material that connects the IC device and the conformable lid is able to be achieved due to the deformable floor deforming or bending along with the IC device.

Abstract: An integrated circuit (IC) device package includes an IC device connected to an upper surface of the IC device carrier. Due to operation conditions or IC device package makeup, the IC device may warp. The warped IC device may include a convex upper surface. A conformable lid is connected to the IC device and includes an internal chamber and a deformable floor. The deformable floor is able to deform or bend along with the IC device. After deformation, the deformable floor may include a concave lower surface. A uniform bond line thickness of a thermal interface material that connects the IC device and the conformable lid is able to be achieved due to the deformable floor deforming or bending along with the IC device.

Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, a first directional heat spreader, and a second directional heat spreader. Presented herein is a fabrication method that includes attaching the stiffening frame to the carrier. The stiffening frame includes a central opening, a base portion, a first pair of opposing sidewalls, and a second pair of opposing sidewalls. The method includes electronically coupling the semiconductor chip to the carrier concentrically arranged within the central opening. The method includes thermally contacting the first directional heat spreader to the semiconductor chip. The first directional heat spreader transfers heat from the semiconductor chip towards the first pair of opposing sidewalls. The method includes thermally contacting the second directional heat spreader to the first directional heat spreader.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned against a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment features within the lid with one or more respective alignment features of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, the lid be loaded against respective IC chips, and the lid may be loaded against the carrier. While under compression, thermal interface material between respective the lid and respective IC chips and seal band material between the lid and the carrier may be cured.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: A method includes electrically connecting an IC chip module to a motherboard and thermally contacting a heat sink to the IC chip module. The IC chip module includes a carrier comprising a top surface and a bottom surface configured to be electrically connected to the motherboard. The IC chip module includes a stiffening frame attached to the carrier top surface. The stiffening frame includes a base portion that has a central opening and a plurality of opposing sidewalls. The IC chip module further includes a semiconductor chip electrically connected to the carrier top surface and concentrically arranged within the central opening. The IC chip module further includes a first directional heat spreader thermally contacting the semiconductor chip. The first directional heat spreader includes a directionally thermally conductive material arranged to efficiently transfer heat from the semiconductor chip in a first opposing bivector direction towards first opposing sidewalls.

Abstract: A multi integrated circuit (IC) chip package includes multiple IC chips, a carrier, and a lid. The IC chips may be connected to the carrier. Alternatively, each IC chip may be connected to an interposer and multiple interposers may be connected to the carrier. The carrier may be positioned within a carrier deck. The lid may be positioned relative to carrier by aligning one or more alignment receptacles within the lid with one or more respective alignment protrusions of the carrier deck. A compression fixture cover may contact the lid and exert a force toward the carrier deck, respective lid pedestals may be loaded toward respective IC chips, and an integral lid foot may be loaded toward the carrier. While under compression, thermal interface material between respective lid pedestals and respective IC chips and seal band material between the integral foot and the carrier may be cured.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: An integrated circuit (IC) chip module includes a carrier, a stiffening frame, an IC chip, and a first directional heat spreader. A second directional heat spreader may further be arranged orthogonal to the first directional heat spreader. The carrier has a top surface and a bottom surface configured to be electrically connected to a motherboard. The stiffening frame includes an opening that accepts the IC chip and may be attached to the top surface of the carrier. The IC chip is concentrically arranged within the opening of the stiffening frame. The first directional heat spreader is attached to the stiffening frame and to the IC chip and generally removes heat in a first opposing bivector direction. When included in the IC chip module, the second directional heat spreader is attached to the stiffening frame and to the first directional heat spreader and generally removes heat in a second opposing bivector direction orthogonal to the first opposing bivector direction.

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Abstract: An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material.

Abstract: A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.

Abstract: A method of fabricating a chip module is presented. The chip module includes a stiffening frame, a directional heat spreader, a carrier, and a semiconductor chip. The stiffening frame is attached to the carrier. The stiffening frame includes a base portion with a central opening to accept a semiconductor chip and a first pair of opposing sidewalls. The semiconductor chip is electronically coupled to the carrier concentrically arranged within the central opening. A first directional heat spreader is thermally coupled to the semiconductor chip. The first directional heat spreader includes directionally thermally conductive material arranged to efficiently transfer heat from the semiconductor chip in a first opposing bivector direction towards the first pair of opposing sidewalls.