Abstract: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

Abstract: A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

Abstract: Methods for multiple level program verify, memory devices, and memory systems are provided. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

Abstract: Methods for multiple level program verify, memory devices, and memory systems are disclosed. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.

Abstract: A selected word line that is coupled to a cell to be programmed is biased during a program operation. The unselected word lines are biased with a negative potential to reduce the cell leakage at programming bit line potential. A programming pulse is applied to the bit line coupled to the cell to be programmed. During verification, the unselected word lines are biased back to ground potential.

Abstract: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.

Abstract: A selected wordline that is coupled to a cell to be programmed is biased during a program operation. The unselected wordlines are biased with a negative potential to reduce the cell leakage at programming bitline potential. A programming pulse is applied to the bitline coupled to the cell to be programmed. During verification, the unselected wordlines are biased back to ground potential.

Abstract: The present invention provides a screen for abnormal cells using the cell transconductance. In one embodiment, a method involves reading cells against an elevated reference current while applying an elevated gate voltage, or alternatively, reading all cells against a standard reference current while applying a nominal or elevated gate voltage, and a reduced drain voltage. The abnormal cells fail this test while normal cells pass.

Abstract: The present invention provides a screen for abnormal cells using the cell transconductance. In one embodiment, a method involves reading cells against an elevated reference current while applying an elevated gate voltage, or alternatively, reading all cells against a standard reference current while applying a nominal or elevated gate voltage, and a reduced drain voltage. The abnormal cells fail this test while normal cells pass.