Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

Abstract: Joint demodulation of a desired transmission and an interfering transmission received from an interfering cell with an unknown combination of transmission parameters is performed. For each subcarrier, an exhaustive search for the serving cell symbols and projection for the interfering cell symbols is performed for tested hypotheses of the interfering cell, by minimizing a whitened noise parabola for each combination of searched hypothesis and hyper constellation point of the serving cell. A constellation point for the interfering cell that is closest to the minimum point of the parabola is selected, where coefficients of the parabola are calculated once for each subgroup of four modulation types of the interfering cell. A measure of likelihood for each of the tested hypotheses is calculated. A cumulative measure of likelihood for each of the tested hypotheses is calculated, and the most likely hypothesis is selected based on the cumulative measure of likelihood.

Abstract: A system and method for performing computational processing by a systolic array. The systolic array including an array of processing elements (PEs) arranged in rows and columns; logic to perform a horizontal shift operation, wherein the horizontal shift operation is performed across the entire systolic array; and logic to mark columns of PEs as enabled or disabled, wherein the systolic array is horizontally divided into horizontal groups, and wherein when performing the horizontal shift operation, valid data that crosses from a first column of PEs of a first horizontal group to a second column of PEs of a second horizontal group is invalidated, wherein the first horizontal group is adjacent to the second horizontal group.

Abstract: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

Abstract: Systems and methods for adaptive demodulation of cellular device communications signals are provided. Cellular communications over a Long Term Evolution network can involve determining a demodulations scheme based on a service cell transmission mode, an interfering cell transmission mode, a modulation order (QAM) of interferer and an interference-to-noise ratio of cellular communications signals.

Abstract: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

Abstract: Joint demodulation of a desired transmission and an interfering transmission received from an interfering cell with an unknown combination of transmission parameters is performed. For each subcarrier, an exhaustive search for the serving cell symbols and projection for the interfering cell symbols is performed for tested hypotheses of the interfering cell, by minimizing a whitened noise parabola for each combination of searched hypothesis and hyper constellation point of the serving cell. A constellation point for the interfering cell that is closest to the minimum point of the parabola is selected, where coefficients of the parabola are calculated once for each subgroup of four modulation types of the interfering cell. A measure of likelihood for each of the tested hypotheses is calculated. A cumulative measure of likelihood for each of the tested hypotheses is calculated, and the most likely hypothesis is selected based on the cumulative measure of likelihood.

Abstract: Systems and methods for adaptive demodulation of cellular device communications signals are provided. Cellular communications over a Long Term Evolution network can involve determining a demodulations scheme based on a service cell transmission mode, an interfering cell transmission mode, a modulation order (QAM) of interferer and an interference-to-noise ratio of cellular communications signals.

Abstract: A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

Abstract: A system and method is provided for executing a conditional branch instruction. The system and method may include a branch predictor to predict one or more instructions that depend on the conditional branch instruction and a branch mis-prediction buffer to store correct instructions that were not predicted by the branch predictor during a branch mis-prediction.

Abstract: A system and method for symmetrical filtering of an input string may include loading, into at least one vector register, in a single read cycle, a subset of right-side data elements and a subset of left-side data elements of the input string. The input string may be stored sequentially in a memory unit. The right-side data elements and the left-side data elements may be equally distant from the center of the input string and may be separated by a whole number of rows in the memory. The system and method may include performing filtering of the input string using a symmetrical filter with the loaded right-side data elements and left-side data elements.

Abstract: A decoder to search a tree graph to decode a received signal. The tree graph may have a plurality of levels, each level having a plurality of nodes and each node representing a different value of an element of a candidate transmit signal corresponding to the received signal. The decoder may include a first module to execute a branch prediction at each branch node to select one of a plurality of candidate nodes stemming from the branch node that has a smallest distance increment, and a second module, running in parallel to the first module, to evaluate the branch prediction made by the first module at each branch node by computing an accumulated distance of the selected node. If the accumulated distance of the selected node is greater than or equal to a search radius, the first module may override the branch prediction and select an alternative candidate node.

Abstract: A decoder to search a tree graph to decode a received signal y. The tree graph may have a plurality of levels, each level having a plurality of nodes and each node representing a different value of an element of a candidate transmit signal s corresponding to the received signal y. The decoder may include a first module to execute a branch prediction at each branch node of the tree graph to select one of a plurality of candidate nodes stemming from the branch node that has a smallest distance increment. The decoder may include a second module, running in parallel to the first module, to evaluate the branch prediction made by the first module at each branch node by computing an accumulated distance of the selected node. If the accumulated distance of the selected node is greater than or equal to a search radius, the first module may override the branch prediction and select an alternative candidate node.

Abstract: Embodiments of the invention are directed to system and method that enable relatively low power dissipation by scheduling operations of multiply accumulators chain of two or more multiply accumulators units by delivering an output result of a first multiply accumulator of the chain as an input to a second subsequent multiply accumulator of the chain.

Abstract: A system and method of data transfer that collapses a multi-dimensional data array while preserving neighboring connectivity. One or more program instructions may be received that request input data comprising a sub-set of data elements from a first data array in an external memory. The sub-set of data elements may be transferred from the first data array in the external memory to a second data array in an internal memory. The retrieved sub-set of requested data elements may be stored in the second array in respective positions translated from the positions in the first array by a plurality of omitted rows and columns from the first data array from which no data elements are requested.

Abstract: A system, processor and method are provided for digital signal processing. A processor may initiate processing a sequence of instructions followed by an interrupt. Each instruction may be processed in respective sequential pipeline slots. A branch detector may detect or determine if an instruction is a branch instruction, for example, in turn, for each sequential instruction. In one embodiment, the branch detector may detect if an instruction is a branch instruction until at least a first branch instruction is detected. A processor may annul instructions which are determined to be branch instructions when the interrupt occupies a delay slot associated with the branch instruction. An execution unit may execute at least the sequence of instructions to run a program. The branch detector and/or execution unit may be integral or separate from each other and from the processor.

Abstract: A system, processor, and method for processing multiple dimension data. A single rectangular data array having a single data port may store a set of data elements representing a multi-dimensional pixel array. A load/store unit may receive the set of data elements and store them divided among a plurality of individually addressable data arrays each having separate address ports. Each individually addressable data array may include at most a single row that stores data elements from a sub-set of the set of data elements representing a multi-dimensional sub-array of the pixel array. A processor may simultaneously access the single row of each of the plurality of individually addressable data arrays by accessing the corresponding respective address ports for each individually addressable data array to retrieve the complete sub-set of data elements in a single computational cycle. An execution unit may execute instruction(s) on the sub-set of data elements.

Abstract: A system and method of data transfer that collapses a multi-dimensional data array while preserving neighboring connectivity. One or more program instructions may be received that request input data comprising a sub-set of data elements from a first data array in an external memory. The sub-set of data elements may be transferred from the first data array in the external memory to a second data array in an internal memory. The retrieved sub-set of requested data elements may be stored in the second array in respective positions translated from the positions in the first array by a plurality of omitted rows and columns from the first data array from which no data elements are requested.

Abstract: A system, processor, and method for filtering multi-dimensional data, for example, image data. A processor may receive an instruction to execute a horizontal filter by combining multi-dimensional data values horizontally aligned in a single row of a first data structure. A second data structure may include a plurality of individually addressable internal memory units. A load unit may load the horizontally aligned values in a transposed orientation for storage as vertically aligned values in a single column in the second data structure in the individually addressable memory units. Each transposed value in the single column may be separately stored in a different respective one of the individually addressable memory units. The processor may independently manipulate and combine each transposed value designated for combination by the horizontal filter by individually accessing the separate memory units.

Abstract: A system, processor, and method for processing multiple dimension data. A single rectangular data array having a single data port may store a set of data elements representing a multi-dimensional pixel array. A load/store unit may receive the set of data elements and store them divided among a plurality of individually addressable data arrays each having separate address ports. Each individually addressable data array may include at most a single row that stores data elements from a sub-set of the set of data elements representing a multi-dimensional sub-array of the pixel array. A processor may simultaneously access the single row of each of the plurality of individually addressable data arrays by accessing the corresponding respective address ports for each individually addressable data array to retrieve the complete sub-set of data elements in a single computational cycle. An execution unit may execute instruction(s) on the sub-set of data elements.