Patents by Inventor Jeffrey Allen Webster

Jeffrey Allen Webster has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming power semiconductor devices with controllable integrated buffer
    Patent number: 5872028
    Abstract: A method of manufacturing a semiconductor device and device in which a sacrificial N shelf layer is grown on a P+ semiconductor substrate to contain the out-diffusion of dopant from the substrate. An N+ buffer layer is grown on the N shelf layer and an N- epitaxial layer is grown on the N+ buffer layer. The presence of the N shelf layer, which is consumed by the substrate dopant during further device fabrication, allows the integrated dopant level of the N+ buffer layer to be accurately controlled in the finished device.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: February 16, 1999
    Assignee: Harris Corporation
    Inventors: Joseph Andrew Yedinak, Anup Bhalla, Jeffrey Allen Webster, Joseph Leonard Cumbo