Abstract: Diffusion regions in a standard cell design are bridged across cell boundaries. Shallow trench isolation is reduced and nitride passivation thickness variation is reduced.

Abstract: Embodiments of the invention include a data buffer for connecting a core of a data circuit to a data pad. External devices may couple to the data pad even if they have a different power supply voltage than does the core of the data circuit. A pass transistor is coupled between the data pad and a data node in the buffer. A control circuit monitors a signal on the data pad and drives the pass transistor according to the signal received, thereby preventing damage due to voltage mismatch between the data circuit and the external device.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: An apparatus and a method for compensating the drain current degradation in pMOS transistors are disclosed. The pMOS transistor receiving drain current compensation is a primary pMOS transistor. The apparatus comprises of a plurality of pMOS transistors subject to drain current degradation correlating to drain current degradation of the primary pMOS transistor, at least one compensation pMOS transistor coupled in parallel with the primary pMOS transistor, and an output voltage decoder to activate one or more of the compensation pMOS transistors to compensate for the drain current degradation of the primary pMOS transistor based on monitored drain current degradation of the plurality of pMOS transistors.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: An apparatus and a method for decreasing the voltage from a source. The apparatus includes a voltage reference source. The voltage reference source is coupled to a first transistor and to a decoupling capacitor. The first transistor is a negative-channel metal oxide (“NMOS”) transistor which has an output voltage equal to a gate source voltage of the NMOS transistor minus an NMOS transistor threshold voltage.

Abstract: A transfer gate or pass gate circuit for transferring logic signals between nodes for a range of available high-potential supply levels. The primary transfer gate is designed to protect against potentials that either exceed either a high-potential or a low-potential level or that undershoot such potential levels. For overshoot (overvoltage) tolerance, this is achieved by coupling a NMOS transistor in parallel with a pair of PMOS transistors that are coupled in series. All three transistors are located between two nodes, either of which can be the input or the output of the transfer gate. The NMOS transistor is designed to be larger than the PMOS transistors and carries most of the transfer capability. The smaller PMOS transistors are designed to eliminate potential drops that would otherwise occur with a single NMOS transistor or with a complementary pair of transistors.

Abstract: A container has a back wall, a pair of opposing side walls extending from the back wall, and a front wall extending between the side walls to define a rectangular sleeve. Apertures are formed in the front wall to enable access within the sleeve. The apertures are separated from one another by a front wall portion. Also, a top and bottom band are formed at the ends of the container. At least one positioning member extends from the front wall. The positioning member extends toward the back wall to maintain an article in position within the container.

Abstract: An electrostatic discharge protection (ESDP) transistor element is coupled at an input or output of an MOS integrated circuit (IC) device for protecting internal transistor elements of the MOS IC device from electrostatic discharge (ESD) dielectric breakdown voltages. A relatively thick passivating layer of low temperature deposited passivating material is deposited over the active area between the channel and gate of the ESDP transistor element. A metal layer gate is formed over the passivating layer. The channel insulating layer thickness provides a turn on voltage V.sub.TON less than the dielectric breakdown voltage BVGOX of internal transistor elements. The bond pads of the MOS IC device are used for the metal layer gates and the metal layer gate bond pads are formed over the active area of the ESDP transistor elements.

Abstract: A transient-eliminating circuit for minimizing simultaneous conduction through the pullup and pulldown transistors of a buffer circuit. In a buffer circuit used to translate logic signals from circuits supplied by one high-potential power rail to circuits supplied by another high-potential power rail, in which the potentials of the two high-potential rails are not equal, the transient-eliminating circuit is coupled between the output stage and the input stage in such a way that the translator can be utilized independent of power-up sequencing and without any static current I.sub.CCt. The transient-eliminating circuit minimizes simultaneous conduction through the pullup and pulldown transistors of the translator by delaying the turn-on of the pulldown transistor until the pullup transistor is completely off.

Abstract: A tristate output buffer circuit provides overvoltage protection from voltage signals on a common bus having a higher voltage level than the internal high potential power rail of the tristate output buffer circuit. A high potential level pseudorail (PV) is coupled to the NWELL of a P channel output pullup transistor (P4). A comparator circuit (P5,P6) couplings the pseudorail (PV) to the output (VOUT). The comparator circuit passgates (P5,P6) are constructed to couple the pseudorail (PV) to the high potential power rail (VCC) for VOUT<VCC and to couple the pseudorail (PV) to the output (VOUT) for VOUT>VCC. A feedback transistor (P1) couples the pseudorail (PV) to an internal node of the tristate output buffer circuit at the control gate node of the output pullup transistor (P4). The feedback transistor (P1) control gate node is coupled to a tristate enable input (EN) for turning on the feedback transistor (P1) during the tristate operating mode and holding off the output pullup transistor (P4).

Abstract: An output buffer circuit reduces switching induced noise in integrated circuit devices. A pulldown feed forward circuit is coupled between the input and the output pulldown transistor. The pulldown feed forward circuit bypasses at least some of the intermediate circuit elements of the output buffer circuit. The pulldown feed forward circuit initiates a relatively small sinking current through the output pulldown transistor in response to a first signal at the input before the intermediate circuit elements initiate relatively large sinking current through the output pulldown transistor means. A pullup feed forward circuit is coupled between the input and the output pullup transistor means. The pullup feed forward circuit bypasses at least some of the intermediate circuit elements of the output buffer circuit.

Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A first output voltage sensing switching circuit is coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements. The secondary pulldown transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer first. A relatively small discharge current is therefore initiated from the output before turn on of the relatively large discharge current of the primary pulldown transistor element.

Abstract: An output buffer for reducing switching induced noise in high speed integrated circuit devices incorporates a relatively small current carrying capacity secondary pulldown transistor element with the current path first and second terminal leads coupled in parallel with the current path first and second terminal leads of the primary pulldown transistor element. A separate pulldown delay resistance element of selected value is coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements. The secondary pulldown transistor element control terminal lead is coupled in the output buffer to receive a signal propagating through the output buffer before the primary pulldown transistor element control terminal lead. A relatively small discharge current is therefore limited from the output before turn on of the relatively large discharge current of the primary pulldown transistor element.