Patents by Inventor Jeffrey B. Reed

Jeffrey B. Reed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118790
    Abstract: A computer readable media, a method, and a system registering a third party application providing an available communication system between a local user and a remote user identity, storing information related to the available communication system in a first database, obtaining contact information for the remote user identity from the third party application, determining a communication type for the third party application, pairing the remote user identity with a contact, and updating a graphical representation of contact information.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 11, 2024
    Inventors: Jeffrey D. Harris, Joseph H. Engel, Keith Stattenfield, John-Peter E. Cafaro, Colter S. Reed, Bruce M. Stadnyk, James C. Wilson, David A. McLeod, Alexander B. Brown
  • Patent number: 8788988
    Abstract: Techniques and structures relating to consistency management for fabrication data are disclosed. A plurality of data sources may contain different values for a variety of design parameters usable by electronic circuit design tools to physically lay out at least a portion of an integrated circuit (such as minimum spacing rules, etc.). By seeking to detect different parameter values and/or parameter values that fail to meet a confidence threshold, potential errors may be uncovered at an earlier stage of the design process. Error detection may occur in response to a request to a database, or as part of a consistency check. Different file formats for different design tools may be imported into a central database to facilitate system operation, and an application programming interface may be used to acquire or calculate data values and perform checks in some embodiments.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 22, 2014
    Assignee: Apple Inc.
    Inventors: Jeffrey B. Reed, Brian J. Nalle, Michael A. Dukes
  • Publication number: 20130111422
    Abstract: Techniques and structures relating to consistency management for fabrication data are disclosed. A plurality of data sources may contain different values for a variety of design parameters usable by electronic circuit design tools to physically lay out at least a portion of an integrated circuit (such as minimum spacing rules, etc.). By seeking to detect different parameter values and/or parameter values that fail to meet a confidence threshold, potential errors may be uncovered at an earlier stage of the design process. Error detection may occur in response to a request to a database, or as part of a consistency check. Different file formats for different design tools may be imported into a central database to facilitate system operation, and an application programming interface may be used to acquire or calculate data values and perform checks in some embodiments.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Inventors: Jeffrey B. Reed, Brian J. Nalle, Michael A. Dukes
  • Patent number: 8397190
    Abstract: A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 12, 2013
    Assignee: Apple Inc.
    Inventors: Robert D. Kenney, Raymond C. Yeung, Paul K. Miller, Donald W. Glowka, Jeffrey B. Reed
  • Patent number: 7219326
    Abstract: The matching algorithm of the layout synthesis method and apparatus disclosed locates transistor pattern matches in a design, links a parameterized tile to each identified match, and adjusts certain variable parameters of the linked parameterized tile to meet the physical design requirements of each located match. Each transistor pattern corresponds to a parameterized tile, which is an actual physical representation of the corresponding pattern and includes variable parameters, which may include transistor size. The matching algorithm locates matches in the design for an ordered list of patterns, names each located match, links the proper parameterized tile to each named match, and adjusts the tile's variable parameters as required. Transistors in the design are included in one and only one named located match.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: May 15, 2007
    Assignee: Intrinsity, Inc.
    Inventors: Jeffrey B. Reed, James S. Blomgren, Donald W. Glowka, Timothy A. Olson, Thomas W. Rudwick
  • Patent number: 4879758
    Abstract: A paging receiver and a method for minimizing spurious interference signals in the radio frequency (RF) stages and the intermediate frequency (IF) stages. The paging receiver includes a receiving means, a timing means, a voltage converting means, and a decoding means. A frequency for the timing signals generated by the timing means is selected to minimize spurious signal response. The timing signals are simultaneously applied to the decoding means and the voltage converting means. The frequency of the timing signal can be varied to minimize spurious signal response. The decoding means is notified of the timing signal frequency to effect the detecting and decoding of received coded information in real time.
    Type: Grant
    Filed: January 2, 1987
    Date of Patent: November 7, 1989
    Assignee: Motorola, Inc.
    Inventors: Michael J. DeLuca, Jeffrey B. Reed
  • Patent number: 4851829
    Abstract: The present invention relates to a paging receiver and a method for generating an alert indicating the status of memory. The paging receiver includes a plurality of memory storage areas, each memory storage storing a received message and including a corresponding value indicative of the status of the stored messages. The status values are priority ordered. The number of memory storage areas having status values not exceeding a first predetermined value is determined. If the number determined is below a second predetermined value, an alert is generated.
    Type: Grant
    Filed: December 4, 1986
    Date of Patent: July 25, 1989
    Assignee: Motorola, Inc.
    Inventors: Michael J. DeLuca, Jeffrey B. Reed