Abstract: A board game and method of play for a game which involves rapid paced action, chance and attention to detail. The board includes a plurality of game cards on a game board having a matrix of number with letters as column headings. Players purchase cards (locations on the board) and have a hand held duplicate for markup. In addition to game cards, players can purchase select special number sequences to win. The game is accelerated by providing a numerical designator adjacent or on the card which is the winning combination of numbers so that the player can see the combination without looking to the matrix of number on card.

Abstract: Method and system for a data transfer operation to a device memory is provided. The method includes setting a counter to an initial value; detecting the data transfer operation; determining if information is written to a first memory location of the device memory; counting in a first direction when a total transfer size (N) is written to the first memory location of the device memory; and counting in a second direction when data is written in memory locations other than the first memory location of the device memory, wherein the data transfer operation is complete when a counter value transitions from a non-initial value to an initial value.

Abstract: A receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. In the described embodiments, a token identifier is an integer value that acts as an index into a token array, which identifies the memory location.

Abstract: Validation of various portions of received data, including validating a cut-through checksum found in a received data packet. The cut-through checksum is based on data found in a packet header, and thus can be validated before the entire packet is received. This feature allows processing of the received data to begin before the entire packet has been received. Many embodiments will also receive a checksum that is based on the entire packet.

Abstract: A node in a network that receives data from a data source, such as another node. The receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. Thus, a token identifier is preferably neither a physical memory address nor a virtual address.

Abstract: A receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. In the described embodiments, a token identifier is an integer value that acts as an index into a token array, which identifies the memory location.

Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: A method for compiling a cycle-based design involves generating a parsed cycle-based design from the cycle-based design, elaborating the parsed cycle-based design to an annotated syntax tree, translating the annotated syntax tree to an intermediate form, and converting the intermediate form to an executable form.

Abstract: A computer system for cycle-based computation includes a processor array, a translation component adapted to translate a cycle-based design, a host computer operatively connected to the processor array and to the translation component, a data connection component interconnecting a plurality of members of the processor array using static routing, a synchronization component enabling known timing relationships among the plurality of members of the processor array, a host service request component adapted to send a host service request from a member of the processor array to the host computer, and an access component adapted to access a portion of a state of the processor array and a portion of a state of the data connection.

Abstract: A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.