Patents by Inventor Jeffrey Bowman Johnson
Jeffrey Bowman Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10325913Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.Type: GrantFiled: January 19, 2018Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: David Paul Brunco, Jeffrey Bowman Johnson
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Publication number: 20180145079Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.Type: ApplicationFiled: January 19, 2018Publication date: May 24, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: David Paul Brunco, Jeffrey Bowman Johnson
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Patent number: 9911740Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.Type: GrantFiled: July 12, 2016Date of Patent: March 6, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: David Paul Brunco, Jeffrey Bowman Johnson
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Publication number: 20180019241Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.Type: ApplicationFiled: July 12, 2016Publication date: January 18, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: David Paul Brunco, Jeffrey Bowman Johnson
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Publication number: 20110278674Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.Type: ApplicationFiled: July 28, 2011Publication date: November 17, 2011Applicant: International Business Machines CorporationInventors: Terence Blackwell Hook, Jeffrey Bowman Johnson, James Spiros Nakos
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Patent number: 8012848Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.Type: GrantFiled: August 16, 2007Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Terence Blackwell Hook, Jeffrey Bowman Johnson, James Spiros Nakos
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Patent number: 7851923Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.Type: GrantFiled: March 25, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Mete Erturk, Robert A. Groves, Jeffrey Bowman Johnson, Alvin Jose Joseph, Qizhi Liu, Edmund Juris Sprogis, Anthony Kendall Stamper
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Publication number: 20090184423Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.Type: ApplicationFiled: March 25, 2009Publication date: July 23, 2009Inventors: Mete Erturk, Robert A. Groves, Jeffrey Bowman Johnson, Alvin Jose Joseph, Qizhi Liu, Edmund Juris Sprogis, Anthony Kendall Stamper
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Patent number: 7563714Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.Type: GrantFiled: January 13, 2006Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: Mete Erturk, Robert A. Groves, Jeffrey Bowman Johnson, Alvin Jose Joseph, Qizhi Liu, Edmund Juris Sprogis, Anthony Kendall Stamper
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Publication number: 20090045468Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Inventors: Terence Blackwell Hook, Jeffrey Bowman Johnson, James Spiros Nakos
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Patent number: 7492048Abstract: Structures and method for forming the same. The semiconductor structure comprises a photo diode that includes a first semiconductor region and a second semiconductor region. The first and second semiconductor regions are doped with a first and second doping polarities, respectively, and the first and second doping polarities are opposite. The semiconductor structure also comprises a transfer gate that comprises (i) a first extension region, (ii) a second extension region, and (iii) a floating diffusion region. The first and second extension regions are in direct physical contact with the photo diode and the floating diffusion region, respectively. The semiconductor structure further comprises a charge pushing region. The charge pushing region overlaps the first semiconductor region and does not overlap the floating diffusion region. The charge pushing region comprises a transparent and electrically conducting material.Type: GrantFiled: January 10, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: James William Adkisson, Jeffrey Peter Gambino, Mark David Jaffe, Jeffrey Bowman Johnson, Jerome Brett Lasky, Richard John Rassel
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Patent number: 7381997Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.Type: GrantFiled: November 26, 2007Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
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Patent number: 7335927Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.Type: GrantFiled: January 30, 2006Date of Patent: February 26, 2008Assignee: Internatioanl Business Machines CorporationInventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
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Publication number: 20070176252Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.Type: ApplicationFiled: January 30, 2006Publication date: August 2, 2007Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
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Patent number: 6812545Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.Type: GrantFiled: April 29, 2003Date of Patent: November 2, 2004Assignee: International Business Machines CorporationInventors: James Stuart Dunn, David L. Harame, Jeffrey Bowman Johnson, Robb Allen Johnson, Louis DeWolf Lanzerotti, Stephen Arthur St. Onge
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Publication number: 20030201517Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to..said substrate surface, wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.Type: ApplicationFiled: April 29, 2003Publication date: October 30, 2003Inventors: James Stuart Dunn, David L. Harame, Jeffrey Bowman Johnson, Robb Allen Johnson, Louis DeWolf Lanzerotti, Stephen Arthur St,. Onge
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Patent number: 6617220Abstract: An epitaxial base bipolar transistor including an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on a portion of the single crystal layer; a raised extrinsic base on a surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein the insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in the single crystal layer, wherein the emitter diffusion has an emitter diffusion junction depth.Type: GrantFiled: March 16, 2001Date of Patent: September 9, 2003Assignee: International Business Machines CorporationInventors: James Stuart Dunn, David L. Harame, Jeffrey Bowman Johnson, Robb Allen Johnson, Louis DeWolf Lanzerotti, Stephen Arthur St. Onge
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Publication number: 20020132438Abstract: An epitaxial base bipolar transistor comprising an epitaxial single crystal layer on a single crystal single substrate; a raised emitter on the semiconductor surface; a raised extrinsic base on the surface of the semiconductor substrate; an insulator between the raised emitter and the raised extrinsic base, wherein said insulator is a spacer; and a diffusion from the raised emitter and from the raised extrinsic base to provide an emitter diffusion and an extrinsic base diffusion in said single crystal substrate, wherein said emitter diffusion has an emitter diffusion junction depth, and wherein said emitter extends to said substrate surface and said base extends to said substrate surface. wherein said emitter to base surface height difference is less than 20% of said emitter junction depth is provided as well as methods for fabricating the same.Type: ApplicationFiled: March 16, 2001Publication date: September 19, 2002Inventors: James Stuart Dunn, David L. Harame, Jeffrey Bowman Johnson, Robb Allen Johson, Louis Dewolf Lanzerotti, Stephen Arthur St. Onge
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Patent number: 5896303Abstract: Disclosed is a method of improved grid generation for semiconductor device simulation. In particular, the invention includes a simple method for locating critical interfaces (e.g., oxide-silicon interfaces) and then utilizing the information to generate finer mesh elements near those boundaries where device behavior is most critical. The method of identifying critical interfaces includes the steps of examining the boundary data for each material region in the device, and then generating normal lines between adjacent boundaries to identify "thin" regions, which are generally associated with the critical interfaces. Once this occurs, a recursive subdivision algorithm may be utilized to generate a grid whose element dimensions are dependent upon their proximity to identified critical regions.Type: GrantFiled: October 11, 1996Date of Patent: April 20, 1999Assignee: International Business Machines CorporationInventors: Stephen Scott Furkay, Jeffrey Bowman Johnson
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Patent number: 5883629Abstract: A method for generating a computer representation of a two-dimensional or three-dimensional object featuring recursive and anisotropic division of the representation. A bitree approach is provided for successively dividing into two equal parts any portion of the computer representation of the object. Each subdivision into two parts is accomplished by dividing the portion either horizontally or vertically. The method is implemented over a user interface to an information handling system comprised of one or more processors, a memory system, I/O devices, and an operating system program. Each subdivision of the computer representation of the object is comprised of a data structure that is efficiently stored in the memory system and dynamically updated to contain information about its neighboring subdivisions in order that balancing can be effectively achieved.Type: GrantFiled: June 28, 1996Date of Patent: March 16, 1999Assignee: International Business Machines CorporationInventor: Jeffrey Bowman Johnson