Abstract: A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.

Abstract: A circuit senses an insertion of an adapter card into a connector coupled to a processor by an MCA bus and signals control logic, which forces all other adapter cards coupled to the MCA bus off of the bus with a preempt signal, driving the bus into an arbitration mode. This may be done while the system is powered. An analog switch divides the preempt signal into one that goes to the adapter cards and a second one that is sent to the processor so that it can perform memory refresh cycles.