Patents by Inventor Jeffrey C. Brownscheidle
Jeffrey C. Brownscheidle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11150909Abstract: In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.Type: GrantFiled: December 11, 2015Date of Patent: October 19, 2021Assignee: International Business Machines CorporationInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
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Patent number: 10942745Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.Type: GrantFiled: September 25, 2018Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 10776122Abstract: Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions.Type: GrantFiled: June 14, 2018Date of Patent: September 15, 2020Assignee: International Business Machines CorporationInventors: Michael J. Genden, Eula Faye Abalos Tolentino, Dung Q. Nguyen, Jeffrey C. Brownscheidle, Tu-An T. Nguyen, David S. Walder
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Patent number: 10740107Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and an instruction sequencing unit. Operation of such a multi-slice processor includes: receiving, at the instruction sequencing unit, a load instruction indicating load address data and a load data length; determining a previous store instruction in an issue queue such that store address data for the previous store instruction corresponds to the load address data, wherein the previous store instruction corresponds to a store data length; and generating, in dependence upon the store data length matching the load data length, an indication in the issue queue that indicates a dependency between the load instruction and the previous store instruction.Type: GrantFiled: June 1, 2016Date of Patent: August 11, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Kurt A. Feiste, Dung Q. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 10719056Abstract: Embodiments herein describe a reservation station (RS) in a processor that merges control data from multiple sources into a merged control data value. Before an instruction issues, the RS gathers and saves control data indicating how the instruction is to be executed. This control data may be saved in control registers. An instruction, however, can update many different types of status control bits in these registers. As such, the RS may store different types of control data for an instruction. Instead of the RS containing multiple registers and data paths for every type of control data, the embodiments herein describe merge logic in the RS that permits control data from different sources to be merged into a single control data value. Once the instruction is issued, the RS passes the merged control data value to an execution unit for processing.Type: GrantFiled: May 2, 2016Date of Patent: July 21, 2020Assignee: International Business Machines CorporationInventors: Brian D. Barrick, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Michael J. Genden, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah
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Publication number: 20190384611Abstract: Embodiments relate to selection and execution of conditional branch instructions. A computer system is configured with a processing core, including an instruction fetch unit and an instruction sequence unit, operatively coupled to memory. The instruction fetch unit fetches instructions from instruction cache and searches the fetched instruction for any conditional branch instructions. For each conditional branch instruction, an associated confidence level assigned to the instruction is obtained. The instruction sequence unit dispatches conditional branch instructions with their confidence level to a branch issue queue (BRQ). In addition, the instruction sequence unit prioritizes the conditional branch instructions in the BRQ based on the assigned confidence level and age, and selects one of the conditional branch instructions.Type: ApplicationFiled: June 14, 2018Publication date: December 19, 2019Applicant: International Business Machines CorporationInventors: Michael J. Genden, Eula Faye Abalos Tolentino, Dung Q. Nguyen, Jeffrey C. Brownscheidle, Tu-An T. Nguyen, David S. Walder
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Patent number: 10445100Abstract: Methods and apparatus for transmitting data between execution slices of a multi-slice processor including receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; calculating a cycle countdown using the latency and the source identifier; determining that the cycle countdown has expired; and in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.Type: GrantFiled: June 9, 2016Date of Patent: October 15, 2019Assignee: International Business Machines CorporationInventors: Salma Ayub, Joshua W. Bowman, Jeffrey C. Brownscheidle, Sundeep Chadha, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 10318294Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.Type: GrantFiled: June 20, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Khandker N. Adeeb, Joshua W. Bowman, Jeffrey C. Brownscheidle, Brandon R. Goddard, Dung Q. Nguyen, Tu-An T. Nguyen, Brian D. Victor, Brendan M. Wong
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Publication number: 20190026113Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.Type: ApplicationFiled: September 25, 2018Publication date: January 24, 2019Inventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 10120693Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.Type: GrantFiled: March 29, 2018Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 10078516Abstract: Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.Type: GrantFiled: August 24, 2015Date of Patent: September 18, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
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Publication number: 20180217843Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.Type: ApplicationFiled: March 29, 2018Publication date: August 2, 2018Inventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 10031757Abstract: Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Such a multi-slice processor includes a plurality of execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Operation of such a multi-slice processor includes, storing, in one or more logical units of a plurality of logical units of an age array, a logical value representing a relative age between instructions; propagating, in response to a current instruction being in a hang state, a hang signal to the plurality of logical units of the age array; in response to the hang signal, generating, from the plurality of logical units, a plurality of logical output values indicating a next instruction ready for execution; and issuing the next instruction for execution.Type: GrantFiled: February 12, 2016Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah
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Patent number: 9996359Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.Type: GrantFiled: April 7, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 9983879Abstract: Operation of a multi-slice processor that includes execution slices implementing dynamic switching of instruction issuance order. Such a multi-slice processor includes determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor; responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions; and responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions.Type: GrantFiled: March 3, 2016Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah
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Patent number: 9971600Abstract: Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.Type: GrantFiled: June 26, 2015Date of Patent: May 15, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
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Patent number: 9965286Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions is represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.Type: GrantFiled: July 27, 2017Date of Patent: May 8, 2018Assignee: International Business Machines CorporationInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
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Patent number: 9880850Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.Type: GrantFiled: May 4, 2016Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
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Patent number: 9870231Abstract: In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.Type: GrantFiled: June 8, 2017Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney, Dung Q. Nguyen
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Publication number: 20170364358Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: KHANDKER N. ADEEB, JOSHUA W. BOWMAN, JEFFREY C. BROWNSCHEIDLE, BRANDON R. GODDARD, DUNG Q. NGUYEN, TU-AN T. NGUYEN, BRIAN D. VICTOR, BRENDAN M. WONG