Abstract: A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.

Abstract: A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.

Abstract: An embodiment for operation of an emulated electrically erasable (EEE) memory system includes a memory controller configured to identify a first quick record of a stack of quick records as a present record, wherein the stack of quick records are stored in a non-volatile portion of memory, the first quick record has a quick record status identifier (ID) that indicates the stack of quick records has not been qualified, determine a record status of a next record after the present record in the non-volatile portion of memory, and in response to a determination that the next record has a blank record status ID: update the next record from the blank record status ID to the quick record status ID, wherein the blank record status ID indicates that the next record is part of the stack of quick records, and qualify the present record using the plurality of program steps.

Abstract: The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.

Abstract: A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. The first plurality and second plurality of programmed bitcells are programmed with a same set of data values. The control circuitry is configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section. The comparator circuitry is configured to compare the first read data to the second read data and generate an error indicator in response to the compare.

Abstract: An embodiment for operation of an emulated electrically erasable (EEE) memory system includes a memory controller configured to identify a first quick record of a stack of quick records as a present record, wherein the stack of quick records are stored in a non-volatile portion of memory, the first quick record has a quick record status identifier (ID) that indicates the stack of quick records has not been qualified, determine a record status of a next record after the present record in the non-volatile portion of memory, and in response to a determination that the next record has a blank record status ID: update the next record from the blank record status ID to the quick record status ID, wherein the blank record status ID indicates that the next record is part of the stack of quick records, and qualify the present record using the plurality of program steps.

Abstract: A method of operating an emulated electrically erasable (EEE) memory system includes entering a quick write mode for a predetermined amount of time, upon detection of imminent power loss of the EEE memory system. A first write request is received immediately subsequent to entering the quick write mode, where the first write request includes a first address of an emulated memory of the EEE memory system and associated first data to be written at the first address. A first new record is created in non-volatile memory of the EEE memory system during the quick write mode, where the first new record includes the first address, the associated first data, and a blank record status identifier. The first new record is updated to have a quick record status ID, in response to a determination that record data of the first new record passes verification.

Abstract: A low semiconductor area impact mechanism for patching operations stored in a boot memory area is provided, thereby providing flexibility to such code. In this manner, current flash memory manager SCRAM, which is used for memory operations when the flash memory is unavailable can be replaced with a significantly smaller register area (e.g., a flip flop array) that provides a small patch space, variable storage, and stack. Embodiments provide such space saving without modification to the CPU core, but instead focus on the external flash memory manager. Patch code can be copied into a designated register space. Since such code used during flash memory inaccessibility is typically small, patching is provided for just a small area of the possible flash memory map, and program flow is controlled by presenting the CPU core's own address to redirect the program counter to the patch area.

Abstract: The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.

Abstract: A method of operating an emulated electrically erasable (EEE) memory system includes entering a quick write mode for a predetermined amount of time, upon detection of imminent power loss of the EEE memory system. A first write request is received immediately subsequent to entering the quick write mode, where the first write request includes a first address of an emulated memory of the EEE memory system and associated first data to be written at the first address. A first new record is created in non-volatile memory of the EEE memory system during the quick write mode, where the first new record includes the first address, the associated first data, and a blank record status identifier. The first new record is updated to have a quick record status ID, in response to a determination that record data of the first new record passes verification.

Abstract: The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.

Abstract: A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. The first plurality and second plurality of programmed bitcells are programmed with a same set of data values. The control circuitry is configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section. The comparator circuitry is configured to compare the first read data to the second read data and generate an error indicator in response to the compare.

Abstract: A brownout tolerant EEPROM emulator (18) manages memory operations at a volatile memory (20) and non-volatile memory (24) using a plurality of sector status bits (451) and forward/reverse skip flags (452, 453) stored in a sector identification record (45) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.

Abstract: Methods and systems are disclosed for code protection in non-volatile memory (NVM) systems. Information stored within NVM memory sectors, such as boot code or other code blocks, is protected using lockout codes and lockout keys written in program-once memory areas within the NVM systems. Further, lockout codes can be combined into a merged lockout code that can be stored in a merged protection register. The merged protection register is used to control write access to protected memory sectors. Lockout code/key pairs are written to the program-once area when a memory sector is protected. The program-once area, which stores the lockout code/key pairs, is not readable by external users. Once protected, a memory sector can not be updated without the lockout code/key pair.

Abstract: The present disclosure provides methods and circuits for managing failing sectors in a non-volatile memory. A record address and a read control signal are received, where the record address identifies a location in the non-volatile memory. The record address is compared with a plurality of dead sector addresses, where the dead sector addresses correspond to a subset of sectors located in the non-volatile memory. Data located at the record address is determined to be invalid in response to a combination of a first detection that the record address matches one of the dead sector addresses and a second detection that the read control signal indicates a read operation is requested to be performed on the non-volatile memory.

Abstract: Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

Abstract: An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.

Abstract: An output circuit, between a first power supply terminal and a second power supply terminal, receives a first logic signal that switches between a first logic state based on a voltage at the first power supply terminal and a second logic state based on a voltage at the second power supply terminal and provides a second logic signal, complementary to the first logic signal. A level translator is in a second power supply domain configured to have a second voltage differential between a third power supply terminal and a fourth power supply terminal, wherein the second voltage differential is greater than the first voltage differential. The level translator is designed so that it may be implemented using a subset of the transistors that have the shortest channel length and narrowest channel width.

Abstract: Methods and systems are disclosed for digital control for regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments dynamically adjust program voltages based upon parameters associated with the cells to be programmed in order to account for IR (current-resistance) voltage drops that occur within program voltage distribution lines. Other voltage variations can also be accounted for with these dynamic adjustments, as well. The parameters for cells to be programmed can include, for example, cell address locations for the cells to be programmed, the number of cells to be programmed, and/or other desired parameters associated with the cells to be programmed. The disclosed embodiments use digital control values obtained from lookup tables based upon the cell parameters to adjust output voltages generated by voltage generation circuit blocks used to program the selected cells thereby tuning the program output voltage level to a predetermined desired level.

Abstract: A method of transferring data from a non-volatile memory (NVM) having a plurality of blocks of an emulated electrically erasable (EEE) memory to a random access memory (RAM) of the EEE includes accessing a plurality of records, a record from each block. A determination is made if any of the data signals of the first data signals are valid and thereby considered valid data signals. If there is only one or none that are valid, the valid data, if any is loaded into RAM and the process continues with subsequent simultaneous accesses. If more than one is valid, then the processes is halted until the RAM is loaded with the valid data, then the method continues with subsequent simultaneous accesses of records.