Patents by Inventor Jeffrey C. Demmin

Jeffrey C. Demmin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5159750
    Abstract: A package for containing an integrated circuit component is provided which includes one or more layers with exposed edges surrounding a central opening. The integrated circuit component is positioned in the central opening. Bond wires connect the bond pads of the integrated circuit component to the continuous shelves of the various stepped-back stadium-like layers as well as to individual insulated leads. The layers are spaced apart by beads or columns of insulative material and the major portion of the layers are separated from each other by a gaseous dielectric, preferably air. The R-C constant is reduced and the speed of transmission is increased by the presence of the low dielectric material providing a device which can function rapidly. The stepped portions of the layers are exposed to allow for electrical interconnections within the layers, as well as from each layer to the integrated circuit.
    Type: Grant
    Filed: April 3, 1991
    Date of Patent: November 3, 1992
    Assignee: National Semiconductor Corporation
    Inventors: Vivek B. Dutta, Jeffrey C. Demmin, Mark L. Diorio, Jon T. Ewanich
  • Patent number: 5146310
    Abstract: A thermally enhanced leadframe having heat conductive paths which thermally couple a die attach pad to thermal connection points spread out as far as possible from each other on the perimeter of the package. The area of the heat conductive path is maximized to occupy substantially all area in the package not occupied by the electrically conductive paths between the wire bond locations and the external connection points such as pins. This configuration maximizes the area of the printed circuit board which is heated thereby increasing thermal cooling efficiency. Further, the leadframe configuration maximizes the area of contact between the integrated circuit package and the heat conductive path thereby increasing the thermal conductivity between the device junctions on the integrated circuit die and the ambient through the material of the package itself.
    Type: Grant
    Filed: July 18, 1991
    Date of Patent: September 8, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Jaime A. Bayan, Jeffrey C. Demmin, Mark L. DiOrio, Young I. Kwon
  • Patent number: 5049976
    Abstract: An integrated circuit package (10) has a layer (22) of silicon positioned between copper die attach pad (18) and silicon integrated circuit die (12). The layer (22) should have a thickness of about half that of the silicon die (12). The layer (22) should also extend symmetrically beyond the die (12). Such an extension provides a horizontal surface beyond the die (12) to which thermosetting encapsulating resin (20) will adhere to produce an enhanced stress reduction effect. Vertical edges (23) of the layer (22) also help to prevent stress of the die (12) by resisting force from the encapsulating resin (20) after it shrinks during curing.
    Type: Grant
    Filed: January 10, 1989
    Date of Patent: September 17, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey C. Demmin, Rajendra D. Pendse
  • Patent number: 5008734
    Abstract: A package for containing an integrated circuit component is provided which includes one or more layers with exposed edges surrounding a central opening. The integrated circuit component is positioned in the central opening. Bond wires connect the bond pads of the integrated circuit component to the continuous shelves of the various stepped-back stadium-like layers as well as to individual insulated leads. The layers are spaced apart by beads or columns of insulative material and the major portion of the layers are separated from each other by a gaseous dielectric, preferably air. The R-C constant is reduced and the speed of transmission is increased by the presence of the low dielectric material providing a device which can function rapidly. The stepped portions of the layers are exposed to allow for electrical interconnections within the layers, as well as from each layer to the integrated circuit.
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: April 16, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Vivek B. Dutta, Jeffrey C. Demmin, Mark L. DiOrio, Jon T. Ewanich