Abstract: Disclosed are exemplary embodiments of electrostatic discharge (ESD) pulse generators that may provide improved system level ESD robustness characterization and qualification analysis.

Abstract: Disclosed are exemplary embodiments of electrostatic discharge (ESD) pulse generators that may provide improved system level ESD robustness characterization and qualification analysis.

Abstract: Disclosed are exemplary embodiments of electrostatic discharge (ESD) pulse generators that may provide improved system level ESD robustness characterization and qualification analysis.

Abstract: Disclosed are exemplary embodiments of transient scanning data visualization methods and systems. Also disclosed are exemplary embodiments of embedded transient scanning systems and methods.

Abstract: Disclosed are exemplary embodiments of transient scanning data visualization methods and systems. Also disclosed are exemplary embodiments of embedded transient scanning systems and methods.

Abstract: Disclosed are exemplary embodiments of systems for creating and dynamically rendering user-adjustable content. Also disclosed are exemplary embodiments of methods for creating and dynamically rendering user-adjustable content.

Abstract: Disclosed are exemplary embodiments of transient scanning data visualization methods and systems. Also disclosed are exemplary embodiments of embedded transient scanning systems and methods.

Abstract: Systems and methods for scanning and characterizing an integrated circuit for transient events. Embedded apparatus can detect transient events that may be incident on the integrated circuit, and moreover, identify particular nodes of the integrated circuit that are affected by the transient event. Additionally, the integrated circuit can be characterized by applying known transient pulses of varying severity to selected nodes of the integrated circuit, detecting the severity levels at which the selected nodes can fail, and storing indications pertaining to pulse severity at which selected nodes can fail. Moreover, based on the characterization, targeted protection mechanisms can be provided for nodes that are characterized as being susceptible.

Abstract: Disclosed are exemplary embodiments of methods and systems for numerical simulation of Electrostatic Discharge (ESD) and Electrical Overstress (EOS) events applied to one or more component devices under test or devices under protection. In an example embodiment, a method generally includes providing access to centralized resources for industry standard nodal circuit or finite element analysis numerical simulation of electromagnetic events, as well as protecting intellectual property for some or all of the numerical models used in the simulation. In an exemplary embodiment, a numerical simulation system provides a platform for multiple users to utilize this platform simultaneously, select independent combinations of models and simulation parameters, execute these simulations and view, and store and retrieve these results independently.

Abstract: The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.

Abstract: A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes.

Abstract: A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes.

Abstract: The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.

Abstract: The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

Abstract: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.

Abstract: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

Abstract: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.

Abstract: The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

Abstract: A programmable timer is disclosed for use in conjunction with a microcontroller circuit. The timer is used as part of a time slice arbiter in a real time operating system, which arbiter manages device routines by allocating them to distinct code time slices executable by such microcontroller. The set up of time slices, including their number, sequence, duration, etc., can be configured and optimized to achieve a desired system performance level based on characteristics of an associated system bus, devices on the bus, etc. The timer operates as a hardware controller to direct the interrupt handler to various entry points in the corresponding routines associated with interrupt based devices on a system bus.

Abstract: An interface that allows the host CPU and the keyboard controller in a PC to share a common BIOS ROM includes a logic circuit that receives a set of input signals and produces a set of signals that emulates a jump instruction op-code that causes the host CPU to vector to a specified address location in the system memory map normally reserved for the system ROM BIOS code, whenever both the host CPU and keyboard controller are contending for access to the BIOS ROM.