Abstract: A mixer circuit (21) includes first (31) and second (32) transconductance amplifiers, a switching circuit (34), and an oscillator processing stage (36). The transconductance amplifiers (31,32) generate differential current signals in response to modulated signals having different carrier frequencies. The oscillator processing stage (36) generates a local oscillator signal from a reference oscillator signal. The switching circuit (34) switches the differential current signals at the frequency of local oscillator signal to generate an intermediate frequency output signal.

Abstract: A radio frequency (RF) switch (40) for use in a wireless communication system operated in a time delay division mode of operation. The switch includes a pair of PIN diodes (54 and 56) serially coupled between the transmitter and receiver paths of the communication system which share a common node (58) to which a bias voltage is provided. The bias voltage is switched between first and second voltage levels to alternately cause one and the other of the pin diodes to be forward biased while the other is reversed bias. In this manner the transmitter and receiver paths will be alternately shorted to alternating current ground while the other path is shorted to a common node to an antenna.

Abstract: A circuit for doubling the frequency of an input signal. The circuit includes a full-wave rectifier that rectifies the input signal to generate an output signal with double the frequency of the input signal. The output signal is compared to a predetermined voltage. Based on this comparison, a control signal is fed back to the full-wave rectifier and the output of the rectifier is adjusted to a predetermined level. In this manner the frequency of the input signal is doubled, and the output power is maintained constant, independent of the input power level.

Abstract: A differential to single-ended converter which combines a pair of applied differential signals of a given frequency applied into a single-ended signal supplied to an output thereof, including capacitive means (14,16 or 36) coupled across a pair of terminals to which the differential signals are applied and transmission line circuitry (18, or 38, 40) coupled across the capacitive means for shifting the phase of one of the differential signals applied to one of the pair of terminals such that it is in phase with the other one of the differential signals applied at the other of the pair of terminals wherein said signals are combined into a single-ended signal and applied to an output of the converter.

Abstract: A frequency translation circuit (10) translates an incoming reference signal (RF.sub.IN) to a lower frequency using a compound mixer circuit (42). The compound mixer circuit (42) has a first mixer circuit (14A) that receives both the incoming reference signal (RF.sub.IN) and a signal generated by a first counter (28A). A second mixer circuit (14X) of the compound mixer circuit (42) receives a signal generated by a second counter (28X) and further translates the signal received from the first mixer circuit (14A) to a lower frequency. Both the first mixer circuit (14A) and the second mixer circuit (14X) generate output signals having a carrier frequency that is lower in frequency by the difference of the two input signals.

Abstract: An image rejection circuit (10) receives an incoming signal (RF.sub.IN) and an oscillator signal (V.sub.OSC) generated by a local oscillator (26). Output signals (I.sub.OUT20 and I.sub.OUT40) are generated by first mixer circuits (14 and 34) by multiplying the incoming signal (RF.sub.IN) with the oscillator signal (V.sub.OSC) Second mixer circuits (24 and 44) multiply the output signals (I.sub.OUT20 and I.sub.OUT40) with a counter signal that is a divided oscillator signal (V.sub.OSC). A summing circuit (46) sums the signals generated by the second mixer circuits (24 and 44) and provides a signal (IF.sub.OUT). Phase shift circuits (22, 29, 31, and 42) provide a shifted oscillator signal (V.sub.OSC) and a shifted counter signal to the first and second mixer circuits (14, 24, 34, and 44) that cause cancellation of unwanted image signals in the signal (IF.sub.OUT).

Abstract: An integrated transceiver circuit (10) includes a single side-band mixer (12) and a phase locked loop (30). The phase locked loop (30) includes a phase detector (32) coupled to a voltage controlled oscillator (36) via a summing circuit (33) and a low pass filter (34). A feedback signal from the voltage controlled oscillator (36) is transferred to the phase detector (32) through a counter (38). Either a phase modulation signal or a frequency modulation signal are inputs of summing circuit (33) and modulate the transmitter carrier signal generated by the voltage controlled oscillator (36). The carrier signal generated at an output terminal (40) of the transmitter tracks the frequency of the local oscillator signal that is supplied at an input terminal of the single side-band mixer (12) in the receiver.

Abstract: A circuit (30) and method for translating a spectrum of a modulated signal. The circuit (30) includes a mixer (33), a summing device (36), and a synthesizer (37). The circuit (30) receives and transmits modulated Radio Frequency (RF) signals. The synthesizer (37) generates a transmitter modulated RF signal (TX.sub.RF) using a modulating signal (TX.sub.MOD). The mixer (33) generates an intermediate frequency signal (IF) by mixing a receiver modulated RF signal (RX.sub.RF) with the transmitter modulated RF signal (TX.sub.RF). The summing device (36) removes modulation of the transmitter modulated RF signal (TX.sub.RF) by combining the intermediate frequency signal (IF) with the modulating signal (TX.sub.MOD).

Abstract: A PLL system (10) includes a PFD (24) that receives a reference clock signal (REF CLK) and a feedback clock signal (FBK CLK). The PFD (24) generates an analog signal (TUNE) based on the phase and frequency relationship of the reference and feedback clock signals. The PFD (24) also generates a clock signal based on two PI phase slips for clocking a counter (70). The analog signal is compared against an upper and lower reference voltage in a threshold detect circuit (34) and the signals UP and DOWN supplied to the counter (70). The counter (70) provides a count value that controls the resonant frequency generated by a tank circuit (73). The tuning range of an oscillator (18) is extended by changing the capacitance of the tank circuit (73).

Abstract: A wireless communication system (10) uses a phase detector (28) having a first pair of flip-flops (50, 56) for detecting the phase difference between an input frequency and a reference frequency. The first pair of flip-flops control current sources (66, 70) in the charge pump of the phase detector to modulate the error signal. A second pair of flip-flops (52, 58) detect when the input frequency is more than 2.pi. ahead of or behind the reference frequency. The second pair of flip-flops increment and decrement a counter (54) which in turn controls additional current sources (78-88) in the charge pump. The additional current sources extend the linear operating range of the error signal when the phase error exceeds .+-.2.pi..

Abstract: A circuit and method for producing a phase shifted quadrature signal (VOUT) from an in-phase signal (VIN). The in-phase signal (VIN) is applied to the control electrode of a voltage follower (121). The voltage follower (121) has a variable output resistance which combines with a capacitor (123) to delay the input signal (VIN) in accordance with the time constant formed by the variable output resistance and the capacitor (123). The variable output resistance is controlled by adjusting the bias current of the voltage follower (121) with a control signal.

Abstract: A low-noise amplifier circuit (40) and a method for generating a bias voltage within the amplifier circuit (40). The amplifier circuit includes a cascode configured circuit (15) having a common emitter transistor (12) biased by a current sourcing circuit (43) and a common base transistor (13) biased by a bias voltage generator (21). The current sourcing circuit (43) measures a base current of the common emitter transistor (12) and transmits the base current to a current mirror (41). Further, a current source (50) transmits a bias current to the current mirror (41). The current mirror sums the currents from the current sourcing circuit (43) and the current mirror (41) and generates a mirror output current. A portion of the mirror output current drives the bias voltage generator (21) and a portion of the mirror output current serves as the base current of the common base transistor (13).

Abstract: An integrated receiver circuit (10) has a first amplifier (12) coupled for receiving a radio frequency (RFIN) input signal. A mixer (16) has an RF input coupled to an output of the first amplifier, a local oscillator (LO) input coupled for receiving an LO signal, and an output for providing an intermediate frequency (IF) signal. A second amplifier (20) has an input coupled for receiving the IF signal, and an output for providing a receive signal strength indicator (RSSI) signal representative of an input power level of the receiver signal path. A feedback circuit (22-26 or 72, 78) is coupled between the first output of the second amplifier and a linearity control input of the mixer for controlling linearity of the mixer.

Abstract: A current regulator (60, 90, and 100) provides current regulation. The current regulator (60, 90, and 100) has a bias generator (14) which compares a generated voltage, V.sub.ref, with a feedback voltage generated in accordance with an output current provided in a reference circuit (57, 58, and 59). The current regulator (60, 90, and 100) operates as a bias circuit to minimize the quiescent currents for efficiently providing regulated output currents in current sink circuit (26). The current in the bias generator (14) and the current in the reference circuit (57, 58, and 59) that regulate the output current in current sink circuit (26) are a small percentage of the overall current.

Abstract: A linear differential gain stage (31) has a first input (32), a second input (33), a first output (34), and a second output (35). A differential input voltage is coupled to an input differential transistor pair (39,40). Voltage compensation circuits (53,54) cancel non-linearities due to the input differential transistor pair (39,40). Parasitic capacitance of the input differential transistor pair (39,40) couple current to the first and second inputs (32,33) due to voltage transitions at the first and second outputs (34,35). The current to the first and second inputs (32,33) is canceled by impedance compensation circuits (55,56) that provide an equal magnitude but opposite sign current. The result is an almost infinite input impedance to the linear differential gain stage (31).

Abstract: A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.

Abstract: A amplifier (21) having increased linearity, low input impedance, and low noise is provided. The amplifier (21) has an input (22), a bias input, a first output (23), and a second output (33). A first transistor (26) has a collector coupled to the first output (23), a base coupled to the bias input, and an emitter. A first resistor (27) is coupled between the emitter of the first transistor (26) and the input (22). A second transistor (29) has a collector and base coupled in common, and an emitter coupled for receiving a power supply voltage. A second resistor (28) couples between the input (22) and the common base and collector of the second transistor (29). A third transistor (32) has a collector coupled to the second output (33), a base coupled to the common base and collector of the second transistor (29), and an emitter coupled for receiving the power supply voltage. An input signal applied to the input (22) generates a differential current at the first and second outputs (23, 33).