Abstract: A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on the location and parasitic elements of the first leaf cell and the location and parasitic elements of the second leaf cell. A parasitic netlist is generated based on the first net segment and the parasitic elements of the first leaf cell and parasitic elements of the second leaf cell.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on the location and parasitic elements of the first leaf cell and the location and parasitic elements of the second leaf cell. A parasitic netlist is generated based on the first net segment and the parasitic elements of the first leaf cell and parasitic elements of the second leaf cell.

Abstract: A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Abstract: A decoder circuit to decode an address for accessing a memory cell in a memory array includes address latch circuitry, inverter circuitry, and first address pre-decode circuitry. The address latch circuitry receives an address signal and generates address holding signals during a setup period. The address latch circuitry latches the address holding signals during an address hold period following the setup period. The inverter circuitry receives the address signal and generates a complementary address signal. The first address pre-decode circuitry decodes the address signal and the address holding signals during the setup period to generate a first pre-decode address signal at an output of the first address pre-decode circuitry. In addition, the first address pre-decode circuitry decodes the address holding signals during the address hold period to maintain the first pre-decode address signal at the output of the first address pre-decode circuitry.

Abstract: An improved floating point unit is disclosed. The floating point unit includes a combined adder-shifter that operates to shift a mantissa portion of at least one floating point operand to align the floating point operand with another floating point operand. The combined adder-shifter includes an adder portion that operates to generate a number of sum bits for exponent difference between the two floating point operands. The adder portion favors generation time performance of lower order ones of the sum bits over generation time performance of higher order ones of the sum bits. The combined adder-shifter also includes a shifter portion that operates to shift the mantissa portion of the at least one floating point operand in accordance with the sum bits.

Abstract: A parallel adder is disclosed. The parallel adder includes a number of computational cells that operate to generate odd sum bits based on generate and propagate terms recursively computed and a plurality of carry-in bits. The parallel adder further includes a number of selection cells that are independent of the computational cells and operate to select and output even sum bits from a number of candidate sum bits, the selection being made in accordance with predetermined ones of said recursively computed generate and propagate terms.

Abstract: A SOI integrated circuit includes a plurality of islands of single crystalline silicon on a surface of a substrate of an insulating material. Each of the silicon islands contains an electrical component, such as a MOS transistor. A layer of silicon oxide is on the surface of the substrate between the islands and is slightly spaced, at least about 0.1 micrometers, from each of the silicon islands. A line of a conductive material, such as conductive polycrystalline silicon, extends over the silicon islands and between the silicon islands over the silicon oxide layer. The silicon oxide layer isolates the conductive line from the substrate so that any photocurrent generated in the substrate as a result of the integrated circuit being exposed to radiation will not flow through the conductive line to disrupt the circuit.