Abstract: A symbology and text generator for use in a graphics rendering processor. The generator accesses font data stored in a processor display memory and generates symbols and text in dot matrix and stroke coded format. A typewriter controller is included which controls symbol and text spacing and live feed functions. The typewriter controller provides for symbol, text, and line of text rotation. Symbol scaling is also provided. A color multiplexer provides for symbols and background field colors. The colors are reversible.

Abstract: An improved graphics processor has rapid response to higher priority tasks. It is implemented with multiple channels of FIFO input circuits and with task interrupt and context switching capability. The graphics processor servicing a first channel task is interrupted when a higher priority task is available in a second channel. Context switching facilitates interrupting of the lower priority first channel task, then saving of the context of the first channel task, then performing higher priority second channel task, then restoring the interrupted first channel task, and then continuing with the processing of the restored first channel task. It is also implemented with concurrent downloading from a host computer and processing by the graphics processor and implemented with general purpose graphics processing capability, including multi-level nested interrupts and nested subroutines.

Abstract: A graphics processor that implements general purpose graphics processing and concurrent DMA display list processing to provide rapid response to display tasks. It is implemented with multiple channels of FIFO input circuits and with task interrupt and context switching circuits. Concurrent with a host processor that constructs and downloads a display list, the graphics processor processes display list instructions as they are downloaded. This reduces latency of the displayed image and facilitates more efficient use of the graphics processor. Implementation of multi-level nested interrupts and nested subroutines by means of interrupt and subroutine circuits further enhances graphics processing capability and enhances response times. Implementation of multiple channels with context switching enhances response times by permitting a higher priority task to interrupt a lower priority task.

Abstract: An integrated hardware generator for generating digital signals representative of vectors, polygons and conics primitives and area fills therefor. The primitive signals are used in the formation of a final digital output signal read into a bit map memory of a graphics display processor. Its operation is based on applying one or more of a set of internal subfunctions to generate mathematical solutions for rendering each geometric shape as a graphics primitive digital signal. The basic building block of the generator is a digital differential analyzer which is adapted to accumulate fractional (subpixel) components of x/y coordinate data and to signal when the accumulation overflows across pixel boundaries. This occurrence enables an increment or decrement of the x/y coordinates that indicate the pixel address to be loaded (drawn). The digital differential analyzer forms an independent vector generator and comprises a pair of input differential multiplexers, an arithmetic logic unit and a register file.

Abstract: Disclosed is a multifunction cogenerator or graphics processor for use in a graphics rendering processor. The graphics processor comprises dual graphics engines operating in parallel, with one of the engines having higher operating priority than the other. The graphics processor comprises a conics, vector, and area fill generator, a symbol generator, a bit block transfer operator, and a block texturing and complex clip mask processor synchronously controlled by a multiprocess scheduler. Included in the graphics processor is a large display memory for receiving and storing program instructions and data generated by an external host processor, internal generators and processors, and a bit mapped memory of a graphics display. The graphics processor provides hardware specific graphics functions and externally programmable general purpose processing.

Abstract: An integrated hardware multiprocess scheduler for controlling a plurality of concurrently operating graphics generating subsystems required for the generation of display signals for a graphics rendering processor. In so doing, the hardware scheduler controls the operations of these subsystems in parallel, while incorporating in hardware, certain aspects of a software operating system. This feature promotes functional independence between the various controlled subsystems and promotes communication between them. Such independence is accomplished by the structure of the scheduler which is set up so that each of the controlled subsystems is connected to a common status/enable bus in parallel with the other controlled subsystems and each of them is operationally independent of the others. Depending on the instructions received, the scheduler enables and disables one or more of these subsystems at essentially the same time.

Abstract: A block texturing and complex clip mask processor for use in a graphics rendering cogenerator. The processor provides two directly accessed texture patterns, and combinational logic for combining texture patterns and graphic primitive signals. The combined texture pattern signals and primitive signals provide for both textured graphic primitives and complex shaped clip mask areas. Also included are inputs for defining rectangular clip masks and logic means for combining the rectangularly clip masks with the texture, graphic primitive and complex clip mask signals.

Abstract: A hardware bit block transfer operator for transferring blocks of data from a source address to a destination address in a display memory, a bit mapped memory, or a host processor, or between the two source and destination addresses in a graphics rendering cogenerator. Functionally, blocks to be transferred are addressable to the bit level thus requiring shifting and reformatting from the source word to the destination word alignment. The cogenerator automatically identifies all required boundary exceptions and applies the appropriate sequencing at the proper time during the block transfer operation. All that the programmer is required to provide are definitions of color depth, source transparency address, source start address, destination transparency address and destination window. The proper transfer is then performed by the cogenerator with a single command to the transfer operator.