Abstract: A resolving system for providing an output clock signal having an output clock frequency that is a predetermined rational multiple of a clock frequency of an input signal to the resolving system. In one embodiment, the resolving system includes a first counter that counts clock pulses of the input clock signal to provide a first value, a second counter that counts clock pulses of the output clock signal to provide a second value, a processor that computes a difference between a ratio of the second and first values with the predetermined rational multiple and generates an error signal based on the difference, and a direct digital synthesis unit that receives the error signal, and based on the error signal generates the output clock signal. In another embodiment, the resolving system, in the absence of an input signal, controls the direct digital synthesis unit to generate the output clock signal at a predetermined frequency.