Abstract: A data processing system (10) includes a CPU (12) connected to a direct-mapped cache (14) by address bus (16) and data bus (18). The cache (14) includes a first-level cache (20) connected to a second-level cache (22) by address bus (24) and data bus (26). The second-level cache (22) of the cache (14) is connected to address bus (28) and data bus (30) by address bus (32) and data bus (34). The address and data busses (28) and (30) are connected to memory (36) and I/O device (41) by address bus (40), data bus (42), address bus (44) and data bus (46), respectively. In the system (10), I/O interface (38) decodes physical memory addresses and responds to addresses in specific ranges using first and second addresses alternately, which are chosen to collide in the data cache (14). I/O software alternates between the two addresses instead of alternating between a device register address and a reserved-region address as in prior art systems.

Abstract: In response to a print request, a print server returns a "window" message which specifies an amount of data that the process is permitted to send to the print server. The amount of data can be zero, indicating that the printer is not available. In this case the print server queues the print request, and when the printer becomes available to service the queued request, the queued request is removed from the queue and a "window" message indicating that the printer is available is sent to the requesting device. In response, the requesting device transmits a packet of data to be printed including the amount of data specified by the window message, and the requesting device waits for an acknowledgement of the print data packet. When the printer finishes printing the data, the print server acknowledges receipt of the data packet, and repeats the window message. This procedure is repeated until the printer has printed all of the data that the requesting device would like to have printed.