Patents by Inventor Jeffrey C. Swanson

Jeffrey C. Swanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180060259
    Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
    Type: Application
    Filed: August 4, 2017
    Publication date: March 1, 2018
    Applicant: Intel Corporation
    Inventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson
  • Publication number: 20180011759
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 11, 2018
    Applicant: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Publication number: 20170308497
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 26, 2017
    Applicant: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson
  • Patent number: 9753885
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Patent number: 9740646
    Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
    Type: Grant
    Filed: December 20, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson
  • Patent number: 9740654
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson
  • Publication number: 20170123894
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Application
    Filed: September 14, 2016
    Publication date: May 4, 2017
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Publication number: 20170109315
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 9626321
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Patent number: 9537665
    Abstract: To address the need for power management, the following facilitates maintaining power states in an efficient manner based at least in part on managing packets at different layers of an input/output interface that supports multiple layers. One specific example prevents a destructive event for link layer control logic because packets and information might have been lost or dropped due to a hang condition and/or a dropped packet. In yet another example of power management, this facilitates a low power platform state by preventing the loss of packets or data upon exiting a platform power state upon initiation of a link reset condition by preventing certain types of packets from reaching link layer controller logic.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Selim Bilgin, Lily P. Looi, Jeffrey C. Swanson
  • Publication number: 20160378711
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 29, 2016
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • Patent number: 9507746
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson
  • Patent number: 9479196
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Patent number: 9444492
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson, Robert J. Safranek
  • Publication number: 20160188500
    Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.
    Type: Application
    Filed: December 25, 2014
    Publication date: June 30, 2016
    Inventors: Brian S. Morris, Jeffrey C. Swanson, Bill Nale, Robert G. Blankenship, Jeff Willey, Eric L. Hendrickson
  • Publication number: 20160179718
    Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.
    Type: Application
    Filed: December 20, 2014
    Publication date: June 23, 2016
    Inventors: Brian S. Morris, Bill Nale, Robert G. Blankenship, Jeffrey C. Swanson
  • Patent number: 9355058
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • Patent number: 9208121
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: December 8, 2015
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • Publication number: 20150261711
    Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
    Type: Application
    Filed: March 16, 2013
    Publication date: September 17, 2015
    Inventors: Jeff WILLEY, Robert G. BLANKENSHIP, Jeffrey C. SWANSON, Robert J. SAFRANEK
  • Publication number: 20150186327
    Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
    Type: Application
    Filed: December 26, 2014
    Publication date: July 2, 2015
    Inventors: Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson