Patents by Inventor Jeffrey Chamberlain

Jeffrey Chamberlain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200311018
    Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Inventors: Tejpal Singh, Yedidya Hilewitz, Ankush Varma, Yen-Cheng Liu, Krishnakanth V. Sistla, Jeffrey Chamberlain
  • Publication number: 20190236038
    Abstract: Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes.
    Type: Application
    Filed: December 20, 2018
    Publication date: August 1, 2019
    Inventors: Swadesh Choudhary, Bahaa Fahim, Doddaballapur Jayashimha, Jeffrey Chamberlain, Yen-Cheng Liu
  • Patent number: 9189296
    Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Bahaa Fahim, Jeffrey Chamberlain, Yen-Cheng Liu
  • Publication number: 20150186191
    Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: INTEL CORPORATION
    Inventors: Bahaa Fahim, Jeffrey Chamberlain, Yen-Cheng Liu
  • Patent number: 8339704
    Abstract: A micro-mirror well. In one embodiment the micro-mirror well includes a plurality of planar mirrors arranged around an axis of symmetry and inclined to form a pyramid well, where each of the plurality of planar mirrors is capable of reflecting light emitting from an object of interest placed inside the pyramid well.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Vanderbilt University
    Inventors: Kevin T. Seale, Ronald S. Reiserer, John P. Wikswo, Sandra Rosenthal, Jeffrey Chamberlain, Charles Wright, Dmitry Markov, Chris Janetopoulos
  • Publication number: 20050158281
    Abstract: The present invention provides systemic nucleic acid sequence delivery without conventional systemic administration aids (SAAs). In certain embodiments, vascular permeability agents (VPAs), such as VEGF, are used in conjunction with nucleic acid viral vectors, such as adeno-associated virus (AAV). The present invention also provides methods of treating disease by co-administration of nucleic cid sequences encoding Igf-1 and dystrophin or dystrophin-like proteins.
    Type: Application
    Filed: November 15, 2004
    Publication date: July 21, 2005
    Applicant: The University of Washington
    Inventors: Jeffrey Chamberlain, Paul Gregorevic, Michael Blankinship, James Allen
  • Publication number: 20050072524
    Abstract: A system, composition, and a method for planarizing or polishing a composite substrate are provided. The planarizing or polishing system comprises (i) a polishing composition comprising (a) about 0.5 wt. % or more of fluoride 5 ions, (b) about 1 wt. % or more of an amine, (c) about 0.1 wt. % or more of a base, and (d) water, and (ii) an abrasive. The present invention also provides a method of planarizing or polishing a composite substrate comprising contacting the substrate with a system comprising (i) a polishing composition comprising (a) about 0.5 wt. % or more of fluoride ions, (b) about 1 wt. % or more of an amine, (c) about 0.1 wt. % or more of a base, and (d) water, and (ii) an abrasive.
    Type: Application
    Filed: September 11, 2003
    Publication date: April 7, 2005
    Applicant: Cabot Microelectronics Corporation
    Inventors: Brian Mueller, Jeffrey Chamberlain, David Schroeder
  • Publication number: 20050049219
    Abstract: The present invention relates to compositions and methods for expressing mini-dystrophin peptides. In particular, the present invention provides compositions comprising nucleic acid sequences that are shorter than wild-type dystrophin cDNA and that express mini-dystrophin peptides that function in a similar manner as wild-type dystrophin proteins. The present invention also provides compositions comprising mini-dystrophin peptides, and methods for expressing mini-dystrophin peptides in target cells.
    Type: Application
    Filed: October 13, 2004
    Publication date: March 3, 2005
    Inventors: Jeffrey Chamberlain, Scott Harper