Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.

Abstract: An apparatus for performing signed and unsigned multiplication is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell, and a selector coupled to each of the computation cell and the compressor. As disclosed, the selector selects and passes either a standard partial product term or an inverse thereof to the compressor, based on whether signed or unsigned multiplication is being performed, respectively, while the compressor compresses the received partial product terms into a pair of partial product terms.

Abstract: An improved method and apparatus for saturation detection in floating point to integer conversions is described. A floating point number is tested for saturation conditions based on an integer field size. From testing the saturation conditions on the floating point number, the present invention predicts whether a floating point number can be converted into an integer value having the given integer field size, or whether the integer field would be saturated. In one embodiment, the saturation conditions are tested on the floating point number in parallel with a floating point to integer conversion.

Abstract: An improved floating point unit (FPU), equipped to perform floating point to integer conversion and integer addition in addition to floating point addition, is described. In one embodiment, the FPU includes a shifter, a bypass datapath, and a bypass multiplexer. The shifter receives an operand input and a control input, and shifts the operand input in accordance with the control input. The bypass datapath bypasses the operand input around the shifter. The bypass multiplexer is coupled to the shifter and the bypass datapath. The bypass multiplexer selects the bypass datapath to enable an integer addition if the operand is an integer operand, and selects the shifter to enable a floating point addition or floating point to integer conversion if the operand is a floating point operand. In an alternate embodiment, the FPU includes an alignment unit, an arithmetic logic unit (ALU), a bypass datapath, and a bypass multiplexer. The alignment unit receives a first input and a second input, and aligns them.