Abstract: An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit.

Abstract: A MOS device includes a set of pMOS transistors on a first side of an IC. The set of pMOS transistors is adjacent to each other in a second direction. The MOS device further includes a set of nMOS transistors on a second side of the IC. The set of nMOS transistors is adjacent to each other in the second direction. The second side is opposite the first side in a first direction orthogonal to the second direction. The MOS device further includes an OD region between the set of pMOS transistors and the set of nMOS transistors. A first set of gate interconnects may extend in the first direction over the OD region. A set of contacts may contact the OD region. The OD region, the first set of gate interconnects, and the set of contacts may form a set of transistors configured as dummy transistors or decoupling capacitors.

Abstract: An integrated circuit, comprising a transistor-based cell comprising a set of fin field effect transistors (Fin FETs) chained together in a first direction, wherein the set of Fin FETs include fins extending longitudinally along the first direction and equally-spaced apart in a second direction orthogonal to the first direction by a fin pitch, and a set of polysilicon gates extending longitudinally along the second direction and equally-spaced apart in the first direction by a poly pitch, wherein a first dimension of the transistor-based cell along the first direction is substantially a first integer multiplied by the poly pitch, and wherein a second dimension of the transistor-based cell along the second direction is substantially a second integer multiplied by the fin pitch. The integrated circuit may include other non-transistor-based cells (e.g., passive cells), such as thin-film resistor or capacitor cells, which are arranged in a two-dimensional array with the transistor-based cell.

Abstract: An integrated circuit, comprising a transistor-based cell comprising a set of fin field effect transistors (Fin FETs) chained together in a first direction, wherein the set of Fin FETs include fins extending longitudinally along the first direction and equally-spaced apart in a second direction orthogonal to the first direction by a fin pitch, and a set of polysilicon gates extending longitudinally along the second direction and equally-spaced apart in the first direction by a poly pitch, wherein a first dimension of the transistor-based cell along the first direction is substantially a first integer multiplied by the poly pitch, and wherein a second dimension of the transistor-based cell along the second direction is substantially a second integer multiplied by the fin pitch. The integrated circuit may include other non-transistor-based cells (e.g., passive cells), such as thin-film resistor or capacitor cells, which are arranged in a two-dimensional array with the transistor-based cell.