Abstract: An integrated wafer probe card with a light source facing a device under test (DUT) side and enabling methodology are provided.

Abstract: A method of forming a wedge-shaped fiber array and a bottom base according to a probing pad layout of a Si-Photonic device to enable optical, DC and RF mixed signal tests to be performed at the same time and the resulting device are provided. Embodiments include a bottom base; and a fiber array with sidewalls and a top surface having a first angle and a second angle, respectively, over the bottom base, wherein the fiber array is structured to expose bond pads of a Si-Photonic device during wafer level Si-Photonic testing.

Abstract: A system for detection of a photon emission generate by a device of an integrated circuit, and methods for detecting the same are provided. The system includes a device space configured to include the device. The system further includes an electrical probe proximate the device space and configured to couple to the device. The electrical probe is configured to induce the device to generate the photon emission. The system further includes an optical fiber having a first end proximate the device space and a second end spaced from the first end. The first end is configured to receive the photon emission generated by the device. The optical fiber is configured to transmit the photon emission from the first end to the second end. The system further includes a detector in communication with the second end of the optical fiber and configured to detect the photon emission transmitted by the optical fiber.

Abstract: A system for detection of a photon emission generate by a device of an integrated circuit, and methods for detecting the same are provided. The system includes a device space configured to include the device. The system further includes an electrical probe proximate the device space and configured to couple to the device. The electrical probe is configured to induce the device to generate the photon emission. The system further includes an optical fiber having a first end proximate the device space and a second end spaced from the first end. The first end is configured to receive the photon emission generated by the device. The optical fiber is configured to transmit the photon emission from the first end to the second end. The system further includes a detector in communication with the second end of the optical fiber and configured to detect the photon emission transmitted by the optical fiber.

Abstract: A test system for testing devices is disclosed. The test system includes a scanning microscope module and a test module. The scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location. The test module includes a tester unit, a reference failure log containing prior failing compare vectors of interest, and a comparator unit which includes a software comparator. The tester unit is configured to perform a test run at the test location of the DUT with a test pattern. If the test run fails testing, the tester unit is configured to compare using the comparator unit to determine if failing test vectors of the test run matches a desired failure signature, and to generate a comparator trigger pulse if failing test vectors match the prior failure signature. The trigger pulse indicates that the test location of the DUT is a failed location.

Abstract: A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time.

Abstract: A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal.

Abstract: A test system for testing devices is disclosed. The test system includes a scanning microscope module and a test module. The scanning microscope module, when testing a device under test (DUT), is configured to perturb the DUT with a laser at a test (pixel) location. The test module includes a tester unit, a reference failure log containing prior failing compare vectors of interest, and a comparator unit which includes a software comparator. The tester unit is configured to perform a test run at the test location of the DUT with a test pattern. If the test run fails testing, the tester unit is configured to compare using the comparator unit to determine if failing test vectors of the test run matches a desired failure signature, and to generate a comparator trigger pulse if failing test vectors match the prior failure signature. The trigger pulse indicates that the test location of the DUT is a failed location.

Abstract: A test system and method for testing integrated circuits with improved defect localization is disclosed. A laser is used to perturb a device under test (DUT) at a test location. A tester tests the DUT with a test pattern and compares test results with compare vectors in a prior failure log. When a failure signature is matched, a failure signal is generated, indicating that the test location is a failed location. Comparing the test results with the compare vectors in the prior failure log and generating the failure signal when the failure signature is detected reduces artifacts from testing, shortening debug turnaround time.

Abstract: A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal.