Abstract: An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.

Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.

Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.

Abstract: An integrated circuit includes a programmable logic circuit and freeze circuitry coupled to receive a freeze signal and a control signal. The integrated circuit also includes a logic circuit coupled to receive an output signal of the programmable logic circuit. The logic circuit is also coupled to receive an output signal of the freeze circuitry. The freeze circuitry causes an output signal of the logic circuit to be in a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit. The integrated circuit also includes clear circuitry that asserts the control signal in response to a clear signal being asserted after the power-up of the integrated circuit. The freeze circuitry causes the output signal of the logic circuit to be in the predefined logic state in response to the control signal being asserted.

Abstract: An integrated circuit device is disclosed that includes an interposer and a programmable fabric die disposed on the interposer. The programmable fabric die includes multiple sectors that each have multiple rows of logic element blocks. Each row of logic element blocks includes multiple microbumps. Each logic element block has programmable fabric circuitry and an input/output interface electrically coupled to a respective microbump. The integrated circuit device also includes a device disposed on the interposer external to the programmable fabric die and electrically coupled to the microbumps via the interposer.

Abstract: An integrated circuit device is disclosed that includes an interposer and a programmable fabric die disposed on the interposer. The programmable fabric die includes multiple sectors that each have multiple rows of logic element blocks. Each row of logic element blocks includes multiple microbumps. Each logic element block has programmable fabric circuitry and an input/output interface electrically coupled to a respective microbump. The integrated circuit device also includes a device disposed on the interposer external to the programmable fabric die and electrically coupled to the microbumps via the interposer.

Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.

Abstract: An integrated circuit may include user storage circuits and scan storage circuits. The scan storage circuits may store data from the user storage circuits and provide the data to a user interface during a read-back operation. The user storage circuits may store data from the scan storage circuits, which the scan storage circuits may have received from the user interface during a write-back operation. The scan storage circuits may be arranged in a scan chain and controlled by a local control circuit. The integrated circuit may include multiple local control circuits that each control a sector of the integrated circuit. The local control circuits may communicate with a global control circuit over a communication network, and the global control circuit may communicate with the user interface.