Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

Abstract: A substantially defect-free, low-k dielectric film having improved adhesion is provided by (a) applying a silane coupling agent containing at least one polymerizable group to a surface of a substrate so as to provide a substantially uniform coating of said silane-coupling agent on said substrate; (b) heating the substrate containing the coating of the silane-coupling agent at a temperature of about 90° C. or above so as to provide a surface containing Si—O bonds; (c) rinsing the heated substrate with a suitable solvent that is effective in removing any residual silane-coupling agent; and (d) applying a dielectric material to the rinsed surface containing the Si—O bonds.

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.

Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type.

Abstract: An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics.

Abstract: A cost effective and simple method of patterning interconnect structures is provided in which spun-on materials are used as the hard mask. The use of spun-on materials for the hard mask ensures that the process is carried out in a single tool and it permits the use of a single curing step which is not typically employed in prior art patterning processes wherein CVD hard masks are employed. The effective dielectric constant of the resultant structure is not significantly increased since the use of spin coating allows for selection of a polish stop layer (formed on a surface of a low-k dielectric) that has substantially the same dielectric constant as the underlying dielectric. In the present invention, the hard mask employed includes at least two spun-on dielectric materials that have different etch rates.

Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics.

Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus achieving a dielectric material that has significantly improved dielectric constant, i.e. smaller than 2.6.

Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.

Abstract: Disclosed is a printed circuit board, and a method of preparing a printed circuit board, which possesses a coefficient of thermal expansion substantially similar to that of silicon for use in direct semiconductor chip attach structures and similar solder mounted devices. The printed circuit board is fabricated from prepreg having a thermosetting resin and a reinforcement layer consisting of non-woven aramid mat or a liquid crystalline polymer paper. The composite dielectric layer optionally includes plated through holes which are either filled or non-filled, and one or more thin film redistribution layers to provide high density electronic packages. The design places the solder pads at the PTHs where needed. The redistribution layer can be formed using photoimagable dielectrics or laminated controlled-CTE composites and laser via imaging.

Abstract: A means to fabricate a color filter for use in a display, such as a liquid crystal display, in which a physical barrier is created which prevents the flow of a liquid dye after application and ensures that individual cells are filled with only the desired color. Additionally, a means is disclosed which creates a surface with all colors initially present, followed by an exposure means and a development means which enables the desired color to fill the desired cell.

Abstract: A composition comprising a thermoset resin which may or may not contain fluorine, bromine or both and containing at least one bromine-containing homo- or multicomponent thermoplastic polymer modifier optionally containing a different halogen which is soluble in the thermoset. Said thermoplastic polymer undergoes an in-situ phase separation process during cure to form a microphase-separated multiphase thermoset material.

Abstract: The invention relates to a process for forming an integrated circuit device comprising (i) a substrate; (ii) metallic circuit lines positioned on the substrate and (iii) a dielectric material positioned on the circuit lines. The dielectric material comprises porous organic polyarylene ether.

Abstract: Methods are described for fabricating devices having vias containing more than one electrical conductor, in particular coaxial electrical conductors. A plurality of wires are bonded to a first substrate, such as a copper wire to a copper substrate. A second substrate having through-holes with side walls covered with an electrical conductor is disposed over the first substrate so that the wires are within the through-holes and spaced apart from the side walls. The first substrate is spaced apart from the second substrate by dielectric spacers. A polymer is injected into the space between the first and second substrates to provide electrical isolation therebetween. A polymer is injected into the space in the via between the elongated conductors and the conductive sidewall to provide dielectric isolation therebetween. The second substrate has electrically conductive pattern on both sides which are electrically interconnected by the electrically conductive sidewall to form an inner coil of electrical conductors.

Abstract: The invention involves a fluid treatment device and fluid treatment method to solution or melt coat or impregnate a resin or polymer to a predetermined, metered thickness into a substrate. The invention is effective in impregnating or coating various substrates in both a continuous or batch process on one side, two sides, or in the case of a porous substrate, penetration and complete saturation is possible. The invention offers significant advantages and benefits over existing methods and equipment and allows the coating or impregnation process to be performed at lower cost and higher efficiency with increased environmental safety.