Abstract: Embodiments are provided in which cache update is implemented by using a counter table having a plurality of entries to keep track of different modified cache lines of a cache of a processor. If a cache line of the cache is modified by the processor and the original content of the cache line came from a cache of another processor, a counter in the counter table restarts and reaches a predetermined value (e.g., overflows) triggering the broadcast of the modified cache line so that the cache of the other processor can snarf a copy of the modified cache line. As a result, when the other processor reads from a memory address matching that of the cache line, the cache of the other processor already has the most current copy for the matching memory address to feed the processor. Therefore, a cache read miss is avoided and system performance is improved.

Abstract: A miniature transformer for use with printed circuit boards includes a winding assembly comprising a first tubular bobbin having a first winding thereon, and second and third tubular bobbins each having a winding thereon and being received, respectively, in the open opposite ends of the first bobbin. A shell member is received over the winding assembly and engages the ends of the second and third bobbins for holding the same within the first tubular bobbin. There are a pair of E-shaped core members each having a center leg received in the open ends of the second and third bobbins and side legs received in a gap between the shell member and the winding assembly.

Abstract: A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.

Abstract: Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.

Abstract: A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.

Abstract: An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.