Patents by Inventor Jeffrey D. David

Jeffrey D. David has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11609812
    Abstract: Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: March 21, 2023
    Assignee: PDF Solutions, Inc.
    Inventors: Richard Burch, Jeffrey D. David, Qing Zhu, Tomonori Honda, Lin Lee Cheong
  • Publication number: 20210142122
    Abstract: Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.
    Type: Application
    Filed: October 14, 2020
    Publication date: May 13, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Tomonori Honda, Richard Burch, John Kibarian, Lin Lee Cheong, Qing Zhu, Vaishnavi Reddipalli, Kenneth Harris, Said Akar, Jeffrey D David, Michael Keleher, Brian Stein, Dennis Ciplickas
  • Publication number: 20210103489
    Abstract: Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.
    Type: Application
    Filed: October 6, 2020
    Publication date: April 8, 2021
    Applicant: PDF Solutions, Inc.
    Inventors: Richard Burch, Jeffrey D. David, Qing Zhu, Tomonori Honda, Lin Lee Cheong
  • Patent number: 8088298
    Abstract: Methods and apparatus for spectrum-based endpointing. An endpointing method includes selecting two or more reference spectra. Each reference spectrum is a spectrum of white light reflected from a film of interest on a first substrate and has a thickness greater than a target thickness. The reference spectra is selected for particular spectra-based endpoint determination logic so that the target thickness is achieved when endpoint is called by applying the particular spectra-based endpoint logic. The method includes obtaining two or more current spectra. Each current spectrum is a spectrum of white light reflected from a film of interest on a second substrate when the film of interest is being subjected to a polishing step and has a current thickness that is greater than the target thickness. The method includes determining, for the second substrate, when an endpoint of the polishing step has been achieved.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: January 3, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Boguslaw A. Swedek, Dominic J. Benvegnu, Jeffrey D. David
  • Patent number: 6361405
    Abstract: A utility wafer, more specifically, an utility wafer for simulating a workpiece in a semiconductor processing system. The utility wafer includes a first side, a second side and a peripheral edge wherein one or both edges of the peripheral edge are relieved to remove the otherwise sharp edge. In one embodiment, the peripheral edge is polished. The utility wafer is resistant to chipping, stress cracking and breakage when undergoing chemical mechanical planarization.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: March 26, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey D. David, Benjamin A. Bonner, Thomas H. Osterheld, Sidney Huey
  • Publication number: 20020028635
    Abstract: A utility wafer, more specifically, an utility wafer for simulating a workpiece in a semiconductor processing system. The utility wafer includes a first side, a second side and a peripheral edge wherein one or both edges of the peripheral edge are relieved to remove the otherwise sharp edge. In one embodiment, the peripheral edge is polished. The utility wafer is resistant to chipping, stress cracking and breakage when undergoing chemical mechanical planarization.
    Type: Application
    Filed: April 6, 2000
    Publication date: March 7, 2002
    Applicant: DAVID et al
    Inventors: Jeffrey D. David, Benjamin A. Bonner, Thomas H. Osterheld, Sidney Huey