Patents by Inventor Jeffrey D. Gilbert
Jeffrey D. Gilbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080109624Abstract: A system and method for providing multiprocessors with private memory are described. In one embodiment, a first chip couples to a plurality of processor chips. In one embodiment, the first chip includes memory management circuitry and system coherency circuitry. In one embodiment, the memory management circuitry assigns segments of memory to be system memory sections or private memory sections within a segment. In one embodiment, the system coherency circuitry maintains coherence of entries in the system memory.Type: ApplicationFiled: November 3, 2006Publication date: May 8, 2008Inventors: Jeffrey D. Gilbert, Stephen R. Wheat, Kai Cheng, Rajesh S. Pamujula
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Publication number: 20080065832Abstract: Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.Type: ApplicationFiled: September 8, 2006Publication date: March 13, 2008Inventors: Durgesh Srivastava, Jeffrey D. Gilbert
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Publication number: 20080005485Abstract: A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a processor. A coherency engine updates the entries in the snoop filter such that an entry is removed from the snoop filter if the entry exits the exclusive state. To ensure data coherency, the coherency engine implements a sequencing rule that decouples a read request from a write request.Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventors: Jeffrey D. Gilbert, Kai Cheng, Liqun Cheng
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Patent number: 7228387Abstract: A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.Type: GrantFiled: June 30, 2003Date of Patent: June 5, 2007Assignee: Intel CorporationInventors: Zhong-Ning Cai, William G. Auld, Jeffrey D. Gilbert
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Patent number: 7124229Abstract: A method and apparatus for improved performance for handling priority agent bus requests when symmetric agent bus parking is enabled is disclosed. In one embodiment, a modified priority agent may be used. The modified priority agent may assert an unused symmetric agent bus request when it asserts its priority agent bus request. When a symmetric agent parks on the bus, continually asserting its symmetric agent bus request, the assertion of the otherwise unused symmetric agent bus request may cause the symmetric agent to withdraw its symmetric agent bus request. This may reduce bus response time for subsequent modified priority agent bus requests.Type: GrantFiled: November 2, 2004Date of Patent: October 17, 2006Assignee: Intel CorporationInventors: Jeffrey D. Gilbert, Harris D. Joyce
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Patent number: 6893948Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: GrantFiled: July 11, 2003Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Publication number: 20040268050Abstract: A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performed by the use of a more efficient prefetching mechanism.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Zhong-Ning Cai, William G. Auld, Jeffrey D. Gilbert
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Patent number: 6822311Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: GrantFiled: April 15, 2003Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Patent number: 6759260Abstract: A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer.Type: GrantFiled: April 23, 2003Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Edward C. Cooney, III, Jeffrey D. Gilbert, Robert G. Miller, Amy L. Myrick, Ronald A. Warren
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Publication number: 20040023476Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: ApplicationFiled: July 11, 2003Publication date: February 5, 2004Applicant: International Business MachinesInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6670263Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: GrantFiled: March 10, 2001Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glen L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Patent number: 6660664Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.Type: GrantFiled: March 31, 2000Date of Patent: December 9, 2003Assignee: International Business Machines Corp.Inventors: James W. Adkisson, Arne W. Ballantine, Matthew D. Gallagher, Peter J. Geiss, Jeffrey D. Gilbert, Shwu-Jen Jeng, Donna K. Johnson, Robb A. Johnson, Glen L. Miles, Kirk D. Peterson, James J. Toomey, Tina Wagner
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Publication number: 20030201515Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: ApplicationFiled: April 15, 2003Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Publication number: 20030183897Abstract: A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer.Type: ApplicationFiled: April 23, 2003Publication date: October 2, 2003Inventors: Arne W. Ballantine, Edward C. Cooney, Jeffrey D. Gilbert, Robert G. Miller, Amy L. Myrick, Ronald A. Warren
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Patent number: 6580140Abstract: A method, and associated structure, for monitoring temperature and temperature distributions in a heating chamber for a temperature range of 200 to 600° C., wherein the heating chamber may be used in the fabrication of a semiconductor device. A copper layer is deposited over a surface of a semiconductor wafer. Next, the wafer is heated in an ambient oxygen atmosphere to a temperature in the range of 200-600° C. The heating of the wafer oxidizes a portion of the copper layer, which generates an oxide layer. After being heated, the wafer is removed and a sheet resistance is measured at points on the wafer surface. Since the local sheet resistance is a function of the local thickness of the oxide layer, a spatial distribution of sheet resistance over the wafer surface reflects a distribution of wafer temperature across the wafer surface during the heating of the wafer.Type: GrantFiled: September 18, 2000Date of Patent: June 17, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Edward C. Cooney, III, Jeffrey D. Gilbert, Robert G. Miller, Amy L. Myrick, Ronald A. Warren
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Patent number: 6552411Abstract: A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.Type: GrantFiled: March 16, 2001Date of Patent: April 22, 2003Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, John J. Ellis-Monaghan, Toshihura Furukawa, Jeffrey D. Gilbert, Glenn R. Miller, James A. Slinkman
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Publication number: 20020182893Abstract: Disclosed is a method to convert a stable silicon nitride film into a stable silicon oxide film with a low content of residual nitrogen in the resulting silicon oxide film. This is an unexpected and unique property of the in situ steam generation process since both silicon nitride and silicon oxide materials are chemically very stable compounds. Application of the claimed method to the art of microelectronic device fabrication, such as fabrication of on-chip dielectric capacitors and metal insulator semiconductor field effect transistors, is also disclosed.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, Johnathan E. Faltermeier, Philip L. Flaitz, Jeffrey D. Gilbert, Oleg Gluschenkov, Carol J. Heenan, Rajarao Jammy, Ryota Katsumada
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Publication number: 20020149064Abstract: Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.Type: ApplicationFiled: March 10, 2001Publication date: October 17, 2002Inventors: Arne W. Ballantine, Kevin K. Chan, Jeffrey D. Gilbert, Kevin M. Houlihan, Glenn L. Miles, James J. Quinlivan, Samuel C. Ramac, Michael B. Rice, Beth A. Ward
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Publication number: 20020106906Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.Type: ApplicationFiled: December 13, 2000Publication date: August 8, 2002Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, Jeffrey S. Brown, Jeffrey D. Gilbert, James J. Quinlivan, James A. Slinkman, Anthony C. Speranza
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Patent number: 6417070Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.Type: GrantFiled: December 13, 2000Date of Patent: July 9, 2002Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Jeffrey S. Brown, Jeffrey D. Gilbert, James J. Quinlivan, James A. Slinkman, Anthony C. Speranza