Patents by Inventor Jeffrey D. Hartman

Jeffrey D. Hartman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9202906
    Abstract: The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 1, 2015
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Robert S. Howell, Eric J. Stewart, Bettina A. Nechay, Justin A. Parke, Harlan C. Cramer, Jeffrey D. Hartman
  • Publication number: 20140264273
    Abstract: The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Robert S. Howell, Eric J. Stewart, Bettina A. Nechay, Justin A. Parke, Harlan C. Cramer, Jeffrey D. Hartman
  • Patent number: 7420226
    Abstract: High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: September 2, 2008
    Assignee: Northrop Grumman Corporation
    Inventors: Godfrey Augustine, Deborah Partlow, Alfred Paul Turley, Thomas Knight, Jeffrey D. Hartman
  • Publication number: 20080157090
    Abstract: An epitaxial layer regrowth method and device. A single crystal seed layer is deposited on a support wafer. An exfoliation layer is implanted in the single crystal seed layer. Trenches are etched in a portion of the single crystal seed layer and a portion of the exfoliation layer. The single crystal seed layer, on the support wafer, is bonded to a substrate. The support wafer and the exfoliation layer are removed leaving behind one or more single crystal seeds, generated from the single crystal seed layer, on the substrate. A first epitaxial layer is grown on the substrate from the single crystal seeds and a device layer is grown on the first epitaxial layer. In an alternative embodiment, a single crystal seed layer is deposited on a support wafer comprising an etch stop.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Darren Brent Thomson, Jeffrey D. Hartman
  • Patent number: 7253083
    Abstract: First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon layer is further reduced by a plasma etch which may leave an uneven thickness. With appropriate masking the uneven thickness is made even by a second plasma etch. Remaining silicon is removed by a dry etch with XeF2 or BrF3 to expose the intermediate oxide layer. Prior to bonding, the semiconductor wafers may be provided with various semiconductor devices to which electrical connections are made through conducting vias formed through the exposed intermediate oxide layer.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: August 7, 2007
    Assignee: Northrop Grumman Corporation
    Inventors: Rowland C. Clarke, Erica C. Elvey, Silai V. Krishnaswamy, Jeffrey D. Hartman