Abstract: In an embodiment, a data processing system comprises a storage system coupled to a unit under test comprising a heap memory, a static memory and a stack; second logic operable to perform: detecting one or more changes in a first state of the heap memory and the static memory; storing, in the storage system, as a state point of the unit under test, the one or more changes in the first state of the heap memory and the static memory; third logic operable to perform: receiving a request to change the memory under test to a particular state point; in response to the request, loading the particular state point from the storage system and applying the state point to the heap memory and the static memory to result in changing the heap memory and the static memory to a second state that is substantially equivalent to the first state.

Abstract: Recording and replaying computer programs includes state synchronization and thread management techniques that facilitate accurately replaying the recorded execution of a multithreaded application program. State synchronization comprises, during execution of an application program in a computer system, detecting an operation of the application program to write a memory; preventing the operation to write the memory; storing a representation of the memory; permitting the operation to write the memory, resulting in written memory; comparing the written memory to the stored representation; and in response to determining that the written memory is different than the stored representation, generating a notification that a memory state synchronization exception occurred.

Abstract: Recording and replaying computer programs includes detecting whether a race condition exists among multiple threads of a multithreaded application program. In an embodiment, detecting race conditions comprises detecting and preventing an operation of a first thread of an application program to read or write a computer memory, wherein the application program executes a plurality of threads; storing an exception point representing a current location in an execution path of the application program; allowing the operation to read or write the memory; creating and storing a record identifying the memory, the first thread, and an index value for a location in the execution path; and determining, based on the record and a plurality of other similar records, whether a race condition exists at the exception point for the first thread and one or more other threads in the plurality of the threads.

Abstract: In an embodiment, a data processing system comprises a storage system coupled to a unit under test comprising a heap memory, a static memory and a stack; second logic operable to perform: detecting one or more changes in a first state of the heap memory and the static memory; storing, in the storage system, as a state point of the unit under test, the one or more changes in the first state of the heap memory and the static memory; third logic operable to perform: receiving a request to change the memory under test to a particular state point; in response to the request, loading the particular state point from the storage system and applying the state point to the heap memory and the static memory to result in changing the heap memory and the static memory to a second state that is substantially equivalent to the first state.

Abstract: A method is disclosed for recording and replaying computer programs. In one embodiment, a method of modifying a computer program to support recording execution, comprises the computer-implemented steps of receiving an executable application binary; modifying the executable application binary by adding one or more proxy code elements to result in creating a modified application binary, wherein upon execution of the modified application binary, the one or more proxy code elements create and store recorded information representing all non-deterministic events that occur during the execution. For example, asynchronous callbacks and thread context switches are recorded and can be replayed.

Abstract: A system, method, and computer program product is presented for simulating a system of hardware components. Each component is simulated in a hardware definition language such as VERILOG. Each component is represented as a simulated device under test (DUT) that is incorporated into a simulation module. The invention synchronizes the simulation modules by issuing clock credit to each simulation module. Each simulation module can only operate when clock credit is available, and can only operate for some number of clock cycles corresponding to the value of the clock credit. Operation is said to consume the clock credit. After a simulation module has consumed its clock credit, its DUT halts. Once every simulation module has consumed its clock credit and halted, another clock credit can be issued. This allows checkpointing of the operation of each DUT and simulates parallelism of the DUTs using executable images of manageable size.