Patents by Inventor Jeffrey David Punzalan

Jeffrey David Punzalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit packaging system with substrate and method of manufacture thereof
    Patent number: 10109587
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: October 23, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
  • Integrated circuit packaging system with interposer structure and method of manufacture thereof
    Patent number: 9659897
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 23, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Integrated circuit packaging system with substrate and method of manufacture thereof
    Patent number: 9412624
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: August 9, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Dao Nguyen Phu Cuong, Bartholomew Liao Chung Foh, Byung Tai Do, Kyung Moon Kim, Jeffrey David Punzalan, SeungYong Chai, Soo Won Lee, Kwok Keung Szeto, KyungOe Kim
  • Integrated circuit packaging system with interposer structure and method of manufacture thereof
    Patent number: 9355983
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Integrated circuit packaging system with coreless substrate and method of manufacture thereof
    Patent number: 9305809
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: April 5, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Allan Pumatong Ilagan, Jeffrey David Punzalan