Abstract: An on-chip optimization circuitry (105) of a semiconductor device (100) provides a delay value to a delay generator (120) indicating an amount to delay an active signal edge. Based on the delay value, a modified device timing is created. Using the modified device timing, a portion of the semiconductor device (130) is tested using on-chip verification circuitry (110) to determine functionality. Based on functionality, a determination is made whether an optimal delay value has been found (550). If an optimal delay value has not been determined, a new delay value is used to produce a new modified device timing (516) and the sequence of testing and determining functionality is repeated until a optimized value has been determined.

Abstract: A latch (40) has a clocked feedback path (46) which performs a static latching function while using less power. The latch includes a feedback device (46) which is selectively decoupled from a feed-forward portion (42, 44) of the latch. In a normal mode of operation when the latch will be clocked often, the feedback device of the latch is not enabled and the latch effectively functions as a dynamic latch. When the latch becomes inactive for an extended period of time, the feedback device is again enabled and the latch is able to store a data value indefinitely.

Abstract: A low power circuit (10) for translating logical addresses or input data to corresponding physical addresses or output data respectively. The circuit (10) includes an input latch (12), content addressable memory (CAM) (14), random access memory (RAM) (16), output latch (18), and comparator (20). The input latch (12) receives the logical address (22) and stores the logical address for at least one comparison cycle. The CAM (14) receives the logical address (22) and produces a corresponding match signal. The RAM (16) receives the corresponding match signal and produces the corresponding physical address (28). The output latch (18) receives the corresponding physical address (28) and stores the value for at least one clock cycle. The comparator (20) enables the CAM (14) and/or the RAM (16) operation only when the previous logical address does not match the current logical address (22).

Abstract: An integrated circuit (20) includes multiple output buffers (30, 50, 70) which switch substantially simultaneously. The output buffers (30, 50, 70) are connected together via a common node (25). Before any one of the output buffers (30, 50, 70) actively drives its corresponding output node to an appropriate logic state, a coupling circuit (42) in the output buffer (30) evaluates whether the new logic state matches the old logic state. If the coupling circuit (42) determines that the logic states are different, then it couples the output node to the common node (25). With each output buffer in the group of multiple output buffers (30, 50, 70) functioning similarly, energy is conserved by using the charge stored in the low-going nodes to charge up the high-going nodes.

Abstract: A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.