Abstract: A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

Abstract: A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

Abstract: An apparatus for managing data queues is disclosed. The apparatus includes at least one sensor for collecting data, a data interface for receiving data from the sensor(s) and for placing the collected data in a set of data queues, and a priority sieve for organizing the set of data queues according to data priority of a specific task. The priority sieve includes a scoreboard for identifying queue priority and a system timer for synchronization.

Abstract: An apparatus for managing data queues is disclosed. The apparatus includes at least one sensor for collecting data, a data interface for receiving data from the sensor(s) and for placing the collected data in a set of data queues, and a priority sieve for organizing the set of data queues according to data priority of a specific task. The priority sieve includes a scoreboard for identifying queue priority and a system timer for synchronization.

Abstract: A compiler method is disclosed which defines a data flow for a specific complex function to be executed on a plurality of data processing elements in a distributed processing system, by means of defining a plurality of control blocks which are associated with each task. The control blocks are in relocatable code so that they may be associated with any one of several similar types of data processing elements within the distributed processing network. The control blocks include local operating system control blocks, token control, post and wait control blocks, and processing element task execution control blocks. The use of the distributed processing system compiler method enables the quick and easy implementation of complex functions having interdependent processing tasks in a distributed processing system.