Abstract: An output buffer generates an output signal having a plurality of low-to-high (LH) and high-to-low (HL) signal transitions, with each of the signal transitions having a clock-to-output delay. A pre-driver having a first and a second stage generates a reshaped waveform to trigger the LH and HL signal transitions of the output signal, with the first stage generating an initial waveform and the second stage modifying the initial waveform to generate the reshaped waveform based at least in part on a feedback reflective of a difference in the clock-to-output delays of the LH and HL signal transitions.

Abstract: An apparatus and method for creating expanded and non-expanded regions on a sheet of sheet metal. The apparatus includes a programmable controller, a sheet metal feeder for incrementally advancing the sheet metal, and a cutter/expander for generating rows of expanded metal apertures. The controller selectively controls both the amount of incremental advance provided to the sheet metal by the feeder and the timing and location of the cutting and expanding provided by the cutter/expander; the combination of which creates such regions.

Abstract: An apparatus and method for creating expanded and non-expanded regions on a sheet of sheet metal. The apparatus includes a programmable controller, a sheet metal feeder for incrementally advancing the sheet metal, and a cutter/expander for generating rows of expanded metal apertures. The controller selectively controls both the amount of incremental advance provided to the sheet metal by the feeder and the timing and location of the cutting and expanding provided by the cutter/expander; the combination of which creates such regions.

Abstract: An on-die termination resistor includes three transistors and a resistor. The resistor keeps at least one of the transistors from entering the saturation region and therefore improves the I-V characteristics of the termination resistor.

Abstract: An integrally molded, repositionable connector has a collapsible obround body that includes lockable annular members that allow the body portion to extend, compress, bend, and lock into selectable lengths and angular positions. Each lockable annular member includes a static side, a movable side, and a reinforcing bead. Each annular member also has a plurality of arcuate segments defining the obround body. The connector can be extended by manually pulling the movable sides away from the static sides until the movable sides lock into position. The connector can also be compressed by pushing the movable sides towards the static sides until the movable sides lock into position.

Abstract: A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.

Abstract: An analog process/voltage/temperature (PVT) compensated buffer includes a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal. The input signal is compatible with a first type of logic. An active gain stage is coupled to translate the first output signal to a second output signal. The second output signal is compatible with a second type of logic. The differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal. In one embodiment, the first type of logic is Gunning Transceiver Logic (GTL) and the second type of logic is complementary metal oxide semiconductor (CMOS) logic.

Abstract: Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity is described. In one embodiment the apparatus includes a first and a second integrated circuit wherein each integrated circuit includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL driver is coupled to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The first and second integrated circuits are cascade-coupled by coupling the first PLL driver of the first integrated circuit to the reference clock signal pin of the second integrated circuit using a propagation path of electrical length L3.

Abstract: Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit.

Abstract: A repositionable downspout extension that is attached to a downspout to direct rainwater away from a building. The extension is a generally tubular body with first and second ends. The extension comprises a pair of selectively removable adapter portions at each end that allow the extension to be connected to a downspout. An interlockable collar portion is at each end of the extension and interior to the adapter portions. The interlockable collar portions allow a number of the extensions to be connected together to form a downspout extension assembly after the adapter portions are removed. The extension further comprises an adjustable portion between the two collar portions. The adjustable portion comprises collapsible corrugations so that the extension can be bent into a number of positions and hold its position.

Abstract: An analog compensation circuit for providing process/voltage/temperature (PVT) bias compensation signals for input/output (I/O) circuitry within an integrated circuit includes a first current source coupled to a first node. A first load coupled to the first current source and a second node provides a first reference voltage. A voltage divider coupled between the first and second nodes provides a current source bias voltage to the first current source. A differential amplifier generates a first bias compensation signal as feedback for the first current source in accordance with the difference between the first reference voltage and a second reference voltage. With the addition of logic level bias converters, the compensation circuitry is capable of providing bias compensation signals to multiple logic families.

Abstract: An apparatus and a method for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity are described. In one embodiment, the apparatus includes a first phase-locked loop (PLL) coupled to a reference clock pin by a path of length L1 and a first PLL feedback pin by a path of length L2 such that L1.apprxeq.L2. In another embodiment, the apparatus includes a second PLL coupled to the reference clock pin by a path of length L3. The second PLL is coupled to an internal core of the integrated circuit by a path of length L4 such that L3.apprxeq.L4. In one embodiment, a computer system incorporating the apparatus includes a first propagation path of length L5 coupled to the first PLL output pin. The first PLL output pin is coupled to the first PLL feedback pin by a path of length L6 such that L5.apprxeq.L6.

Abstract: A thrust bearing for bearing a load along a force vector includes at least two roller elements in rolling contact with one another and arranged along the force vector such that the load is borne through the roller elements. The roller elements are retained within a retainer such that they remain aligned along the force vector while subjected to loads. The retainer used to house the roller elements may be designed to abut the roller elements at minimum points of contact, or alternatively to distribute the load borne by one or both of the roller elements across a greater surface area. One application of the preferred thrust bearings is in an apparatus such as a keyboard support for reducing repetitive stress injuries. A main disk is rotatably coupled to a base and supports a support member on a plurality of the thrust bearings.

Abstract: A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.

Abstract: A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus.

Abstract: A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry.

Abstract: A thrust bearing for bearing a load along a force vector includes at least two roller elements in rolling contact with one another and arranged along the force vector such that the load is borne through the roller elements. The roller elements are retained within a retainer such that they remain aligned along the force vector while subjected to loads. The retainer used to house the roller elements may be designed to abut the roller elements at minimum points of contact, or alternatively to distribute the load borne by one or both of the roller elements across a greater surface area. One application of the preferred thrust bearings is in an apparatus such as a keyboard support for reducing repetitive stress injuries. A main disk is rotatably coupled to a base and supports a support member on a plurality of the thrust bearings.

Abstract: A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry.

Abstract: A flip-flop circuit is described. The flip-flop circuit receives the data signal from a data input, receives a trigger signal from a trigger input, generates a pulse signal in response to an edge in the trigger signal, and stores the data signal in response to the pulse. Alternatively, the flip-flop circuit receives a data signal through a data input, receives a trigger signal through a trigger input, stores the data signal in a latch, and suppresses the trigger signal to the latch when the data signal stored in the latch corresponds to the data signal received through the data input.

Abstract: A method and apparatus for providing a clock noise filter are described. The clock noise filter uses a transparent latch which has a trigger input and a data input. The data input is coupled to receive an input clock signal to be filtered. The output of the latch is the filtered clock signal. The filtered clock signal has a logic state which corresponds to the logic state of the input clock signal when the trigger input has a first predetermined logic state, and the filtered clock signal is inhibited from changing logic state when the trigger input has a second predetermined logic state. A trigger circuit is provided which has an input coupled to the output of the latch and an output coupled to the trigger input of the latch. The trigger circuit outputs the second predetermined logic state to the trigger input of the latch for a time interval in response to a change in logic state of the filtered clock signal and outputs the first predetermined logic state after the time interval has expired.