Patents by Inventor Jeffrey Eastlack

Jeffrey Eastlack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
    Publication number: 20240078211
    Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 7, 2024
    Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
  • Accelerator architecture on a programmable platform
    Patent number: 11797473
    Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 24, 2023
    Assignee: Altera Corporation
    Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
  • ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
    Publication number: 20190065188
    Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 28, 2019
    Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
  • Accelerator architecture on a programmable platform
    Patent number: 10095647
    Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: October 9, 2018
    Assignee: Altera Corporation
    Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack
  • ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
    Publication number: 20150347338
    Abstract: An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
    Type: Application
    Filed: May 29, 2015
    Publication date: December 3, 2015
    Inventors: David Shippy, Martin Langhammer, Jeffrey Eastlack