Abstract: The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a set of one or more units at a first level of a configurable hardware system design hierarchy into a set of two or more units of a lower level of the hardware system design hierarchy. The set of one or more units at a first level includes one or more units dynamically instantiated at design creation time as well as at least a first unit composed of a previously instantiated hardware system composed with two or more levels of units within the hardware system design hierarchy of the previously instantiated hardware system.

Abstract: The present invention includes a method and apparatus for decomposing and verifying configurable hardware. In one embodiment, the method includes automatically decomposing a hardware system into a set of one or more units, creating a testbench for each of the set of units, and verifying each of the set of units before verifying the hardware system design.

Abstract: Various methods and apparatuses are described in which a software programming interface connects one or more functional checker components and one or more protocol checker components to an interconnect monitor component. A computer readable medium stores code for the one or more functional checker components for Intellectual Property (IP) cores, one or more protocol checker components, the interconnect monitor component, and the software programming interface. The monitor component has code to build data structures containing protocol data types requested by a checker component and code on where to deliver data based upon a particular type of data requested by the checker component.

Abstract: An apparatus having a first and second bus is disclosed. In one embodiment, multiple units are coupled to the first and second buses. The units include a middle unit and two side units. Each side unit has a first bus output coupled to a first bus input of the middle unit. The middle unit has a second bus output coupled to a second bus input of each side unit.

Abstract: An apparatus having a first and second bus is disclosed. In one embodiment, multiple units are coupled to the first and second buses. The units include a middle unit and two side units. Each side unit has a first bus output coupled to a first bus input of the middle unit. The middle unit has a second bus output coupled to a second bus input of each side unit.

Abstract: A system and method that enables a user to design and use an Integrated Circuit (IC) simulation model without having access to confidential information contained within the model. In one embodiment the system includes a secure section where confidential simulation model information is contained and accessed. The user does not have access to this secure section. The user is provided access to the system via a user-interaction section, which provides controlled access to the IC model. The user can then establish and initiate simulations of the IC model, selecting test stimulus associated with the cores used within the IC model.