Patents by Inventor Jeffrey ERIC

Jeffrey ERIC has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12456400
    Abstract: A circuit device includes a storing section configured to store a rendering image and a warp processing section. The warp processing section includes a coordinate converting section, a coordinate-address converting section, and an output section. The coordinate converting section converts, with coordinate conversion based on warp parameters and rotation correction parameters, an output coordinate, which is a coordinate on a display image, into an input coordinate, which is a coordinate on the rendering image. The coordinate-address converting section converts the input coordinate into a read address of the storing section. The output section reads out pixel data of the rendering image from the read address of the storing section and outputs, based on the read-out pixel data, pixel data in the output coordinate of the display image.
    Type: Grant
    Filed: June 5, 2024
    Date of Patent: October 28, 2025
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yasutoshi Akiba, Jeffrey Eric
  • Patent number: 12406326
    Abstract: A circuit apparatus includes a memory unit and a warp processing unit. The memory unit stores a warp object image. The warp processing unit performs warp processing on the warp object image and generates a display image displayed in a display area. The warp processing unit performs the warp processing on an image of a first view object of the warp object image based on a first warp parameter for vibration correction and distortion correction. Further, the warp processing unit performs the warp processing on an image of a second view object of the warp object image based on a second warp parameter for the distortion correction.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: September 2, 2025
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yasutoshi Akiba, Kumar Anandabairavasamy Anand, Jeffrey Eric
  • Patent number: 12400318
    Abstract: A circuit device includes a storage circuit, an image conversion circuit, and an error detection circuit. The storage circuit stores received first image data. The image conversion circuit executes an image conversion by a coordinate conversion on the first image data by outputting a reference coordinate indicating a pixel position on the first image data and outputting second image data based on pixel data that is read from the storage circuit based on the output reference coordinate. The error detection circuit executes error detection on the reference coordinate output by the image conversion circuit.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: August 26, 2025
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yasutoshi Akiba, Jeffrey Eric
  • Publication number: 20250053486
    Abstract: A control system includes: an image processing circuit; a first error detection circuit configured to perform first error detection on second image data; a first error code value generation circuit configured to generate a first error code value based on the second image data; a transmission interface circuit; a reception interface circuit; a second error code value generation circuit configured to generate a second error code value based on the second image data; a second error detection circuit configured to perform second error detection based on the first error code value and the second error code value; and a control circuit configured to output a control signal when an error is detected in at least one of the first error detection and the second error detection.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Yasutoshi AKIBA, Jeffrey ERIC
  • Patent number: 12210426
    Abstract: A control system includes: an image processing circuit; a first error detection circuit configured to perform first error detection on second image data; a first error code value generation circuit configured to generate a first error code value based on the second image data; a transmission interface circuit; a reception interface circuit; a second error code value generation circuit configured to generate a second error code value based on the second image data; a second error detection circuit configured to perform second error detection based on the first error code value and the second error code value; and a control circuit configured to output a control signal when an error is detected in at least one of the first error detection and the second error detection.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: January 28, 2025
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yasutoshi Akiba, Jeffrey Eric
  • Publication number: 20240321154
    Abstract: A circuit device includes a storing section configured to store a rendering image and a warp processing section. The warp processing section includes a coordinate converting section, a coordinate-address converting section, and an output section. The coordinate converting section converts, with coordinate conversion based on warp parameters and rotation correction parameters, an output coordinate, which is a coordinate on a display image, into an input coordinate, which is a coordinate on the rendering image. The coordinate-address converting section converts the input coordinate into a read address of the storing section. The output section reads out pixel data of the rendering image from the read address of the storing section and outputs, based on the read-out pixel data, pixel data in the output coordinate of the display image.
    Type: Application
    Filed: June 5, 2024
    Publication date: September 26, 2024
    Inventors: Yasutoshi AKIBA, Jeffrey ERIC
  • Publication number: 20240265488
    Abstract: A circuit apparatus includes a memory unit and a warp processing unit. The memory unit stores a warp object image. The warp processing unit performs warp processing on the warp object image and generates a display image displayed in a display area. The warp processing unit performs the warp processing on an image of a first view object of the warp object image based on a first warp parameter for vibration correction and distortion correction. Further, the warp processing unit performs the warp processing on an image of a second view object of the warp object image based on a second warp parameter for the distortion correction.
    Type: Application
    Filed: March 27, 2024
    Publication date: August 8, 2024
    Inventors: Yasutoshi AKIBA, Kumar Anandabairavasamy ANAND, Jeffrey ERIC
  • Patent number: 12020605
    Abstract: A circuit device includes a storing section configured to store a rendering image and a warp processing section. The warp processing section includes a coordinate converting section, a coordinate-address converting section, and an output section. The coordinate converting section converts, with coordinate conversion based on warp parameters and rotation correction parameters, an output coordinate, which is a coordinate on a display image, into an input coordinate, which is a coordinate on the rendering image. The coordinate-address converting section converts the input coordinate into a read address of the storing section. The output section reads out pixel data of the rendering image from the read address of the storing section and outputs, based on the read-out pixel data, pixel data in the output coordinate of the display image.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: June 25, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yasutoshi Akiba, Jeffrey Eric
  • Patent number: 11983838
    Abstract: A circuit apparatus includes a memory unit and a warp processing unit. The memory unit stores a warp object image. The warp processing unit performs warp processing on the warp object image and generates a display image displayed in a display area. The warp processing unit performs the warp processing on an image of a first view object of the warp object image based on a first warp parameter for vibration correction and distortion correction. Further, the warp processing unit performs the warp processing on an image of a second view object of the warp object image based on a second warp parameter for the distortion correction.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: May 14, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yasutoshi Akiba, Kumar Anandabairavasamy Anand, Jeffrey Eric
  • Patent number: 11707984
    Abstract: A circuit device 100 includes an error detection circuit 110 and a processing circuit 120. The error detection circuit 110 obtains a glare index value, which is an index value indicating glare of a head-up display, based on image data IMD for head-up display. The error detection circuit 110 determines whether or not a glare index value has exceeded a first threshold value, and when the glare index value exceeds the first threshold value, detects occurrence of a first glare error. When occurrence of a first glare error is detected, the processing circuit 120 performs processing corresponding to the first glare error.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 25, 2023
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kumar Anandabairavasamy Anand, Wittmeir Manfred, Jeffrey Eric, Tetsuo Kawamoto, Yasutoshi Akiba
  • Publication number: 20230073794
    Abstract: A control system includes: an image processing circuit; a first error detection circuit configured to perform first error detection on second image data; a first error code value generation circuit configured to generate a first error code value based on the second image data; a transmission interface circuit; a reception interface circuit; a second error code value generation circuit configured to generate a second error code value based on the second image data; a second error detection circuit configured to perform second error detection based on the first error code value and the second error code value; and a control circuit configured to output a control signal when an error is detected in at least one of the first error detection and the second error detection.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 9, 2023
    Inventors: Yasutoshi AKIBA, Jeffrey ERIC
  • Publication number: 20230070936
    Abstract: A circuit device includes a storage circuit, an image conversion circuit, and an error detection circuit. The storage circuit stores received first image data. The image conversion circuit executes an image conversion by a coordinate conversion on the first image data by outputting a reference coordinate indicating a pixel position on the first image data and outputting second image data based on pixel data that is read from the storage circuit based on the output reference coordinate. The error detection circuit executes error detection on the reference coordinate output by the image conversion circuit.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 9, 2023
    Inventors: Yasutoshi AKIBA, Jeffrey ERIC
  • Publication number: 20220392380
    Abstract: A circuit device includes a storing section configured to store a rendering image and a warp processing section. The warp processing section includes a coordinate converting section, a coordinate-address converting section, and an output section. The coordinate converting section converts, with coordinate conversion based on warp parameters and rotation correction parameters, an output coordinate, which is a coordinate on a display image, into an input coordinate, which is a coordinate on the rendering image. The coordinate-address converting section converts the input coordinate into a read address of the storing section. The output section reads out pixel data of the rendering image from the read address of the storing section and outputs, based on the read-out pixel data, pixel data in the output coordinate of the display image.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Yasutoshi AKIBA, Jeffrey ERIC
  • Patent number: 11393066
    Abstract: A display system (100) includes a rendering image generation unit (120), a parameter computation unit (140), and a warp processing unit (130). The parameter computation unit (140) computes a latency compensation parameter for compensating a latency including a rendering processing latency of a rendering image based on tracking information. The warp processing unit (130) performs latency compensation processing for compensating the position of a virtual object in a display region based on the latency compensation parameter.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 19, 2022
    Inventors: Jeffrey Eric, Tetsuo Kawamoto, Wittmeir Manfred, Yosuke Tanikawa, Kumar anandabairavasamy Anand
  • Publication number: 20220101487
    Abstract: A circuit apparatus includes a memory unit and a warp processing unit. The memory unit stores a warp object image. The warp processing unit performs warp processing on the warp object image and generates a display image displayed in a display area. The warp processing unit performs the warp processing on an image of a first view object of the warp object image based on a first warp parameter for vibration correction and distortion correction. Further, the warp processing unit performs the warp processing on an image of a second view object of the warp object image based on a second warp parameter for the distortion correction.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 31, 2022
    Inventors: Yasutoshi AKIBA, Kumar Anandabairavasamy ANAND, Jeffrey ERIC
  • Patent number: 11180026
    Abstract: A circuit device includes an image processing circuit and a comparison circuit. The image processing circuit performs a first mapping process and a first rotation process on an input image to generate an image for a head up display. The image processing circuit performs, on an image, a second mapping process that is a reverse mapping process of the first mapping process and a second rotation process that is a reverse rotation process of the first rotation process to generate an image. The comparison circuit performs a comparison between the image and the image and outputs a result of the comparison as information for detecting an error in the image.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 23, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kumar Anandabairavasamy Anand, Wittmeir Manfred, Jeffrey Eric, Tetsuo Kawamoto, Yasutoshi Akiba
  • Patent number: 11055833
    Abstract: Provided is a circuit device that can appropriately detect an error in a display image in a head up display, an electronic apparatus, an error detection method, and the like. The circuit device includes an image processing circuit and a comparison circuit. The image processing circuit performs first mapping processing, which maps an input first image on a second image to be projected onto a projection target object, and second mapping processing, which converts the second image to a third image. The second mapping processing is reverse mapping processing of the first mapping processing. The comparison circuit performs comparison between the first image and the third image, and outputs the result of comparison as information for performing error detection on the second image.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 6, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kumar anandabairavasamy Anand, Wittmeir Manfred, Jeffrey Eric
  • Publication number: 20210201442
    Abstract: A display system (100) includes a rendering image generation unit (120), a parameter computation unit (140), and a warp processing unit (130). The parameter computation unit (140) computes a latency compensation parameter for compensating a latency including a rendering processing latency of a rendering image based on tracking information. The warp processing unit (130) performs latency compensation processing for compensating the position of a virtual object in a display region based on the latency compensation parameter.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 1, 2021
    Inventors: Jeffrey ERIC, Tetsuo KAWAMOTO, Wittmeir MANFRED, Yosuke TANIKAWA, Kumar anandabairavasamy Anand
  • Patent number: 11010866
    Abstract: A circuit device (100) includes a coordinate transform circuit (20) and a mapping processing circuit (30). The coordinate transform circuit (20) performs coordinate transformation from an input coordinate (IXY1) to an output coordinate (QXY1). The mapping processing circuit (30) generates a second image (IMG2) to be displayed in a display panel for displaying an image in a curved screen display by performing mapping processing on a first image (IMG1) that is input based on the output coordinate (QXY1). The coordinate transform circuit (20) performs the coordinate transformation from the input coordinate (IXY1) to the output coordinate (QXY1) by performing computation processing using a second or more order polynomial representing the coordinate transformation.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 18, 2021
    Inventors: Jeffrey Eric, Kumar Anandabairavasamy Anand, Yasutoshi Akiba
  • Publication number: 20200342567
    Abstract: A circuit device (100) includes a coordinate transform circuit (20) and a mapping processing circuit (30). The coordinate transform circuit (20) performs coordinate transformation from an input coordinate (IXY1) to an output coordinate (QXY1). The mapping processing circuit (30) generates a second image (IMG2) to be displayed in a display panel for displaying an image in a curved screen display by performing mapping processing on a first image (IMG1) that is input based on the output coordinate (QXY1). The coordinate transform circuit (20) performs the coordinate transformation from the input coordinate (IXY1) to the output coordinate (QXY1) by performing computation processing using a second or more order polynomial representing the coordinate transformation.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 29, 2020
    Inventors: Jeffrey ERIC, Kumar Anandabairavasamy ANAND, Yasutoshi AKIBA