Patents by Inventor Jeffrey Frederiksen

Jeffrey Frederiksen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11847058
    Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Laurent Isenegger, Dhawal Bavishi, Jeffrey Frederiksen
  • Publication number: 20220382677
    Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.
    Type: Application
    Filed: August 8, 2022
    Publication date: December 1, 2022
    Inventors: Laurent Isenegger, Dhawal Bavishi, Jeffrey Frederiksen
  • Patent number: 11442867
    Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Laurent Isenegger, Dhawal Bavishi, Jeffrey Frederiksen
  • Patent number: 11094356
    Abstract: A memory system comprises a first memory device and a processing device operatively coupled to the first memory device. The processing device is configured to determine whether to execute a write cycle, at the first memory device, to write data from a second memory device to the first memory device based on persisted data stored by the first memory device.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Frederiksen
  • Publication number: 20200273506
    Abstract: A memory system comprises a first memory device and a processing device operatively coupled to the first memory device. The processing device is configured to determine whether to execute a write cycle, at the first memory device, to write data from a second memory device to the first memory device based on persisted data stored by the first memory device.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Inventor: Jeffrey Frederiksen
  • Patent number: 10714176
    Abstract: Aspects of the present disclosure configure a media controller of a memory component to skip execution of a read-write cycle for specific data if the media controller has not observed at least one prior data modification request from a memory sub-system controller that causes modification of the specific data. For example, a media controller of a first memory component can be configured to include a data modification tracker to monitor a memory channel for data modification requests to a second memory component and to track data modification requests that have been observed by the media controller on the memory channel, where the memory channel may be one shared by the first and second memory components.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Frederiksen
  • Publication number: 20200201776
    Abstract: A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Inventors: Laurent Isenegger, Dhawal Bavishi, Jeffrey Frederiksen
  • Patent number: 10672440
    Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Frederiksen
  • Publication number: 20200058353
    Abstract: Aspects of the present disclosure configure a media controller of a memory component to skip execution of a read-write cycle for specific data if the media controller has not observed at least one prior data modification request from a memory sub-system controller that causes modification of the specific data. For example, a media controller of a first memory component can be configured to include a data modification tracker to monitor a memory channel for data modification requests to a second memory component and to track data modification requests that have been observed by the media controller on the memory channel, where the memory channel may be one shared by the first and second memory components.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventor: Jeffrey Frederiksen
  • Publication number: 20200058334
    Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.
    Type: Application
    Filed: September 16, 2019
    Publication date: February 20, 2020
    Inventor: Jeffrey Frederiksen
  • Patent number: 10446203
    Abstract: Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jeffrey Frederiksen