Abstract: A remote display synchronization technique preserves the presence of a local display device for a remotely-rendered video stream. A server and a client device cooperate to dynamically determine a target frame rate for a stream of rendered frames suitable for the current capacities of the server and the client device and networking conditions. The server generates from this target frame rate a synchronization signal that serves as timing control for the rendering process. The client device may provide feedback to instigate a change in the target frame rate, and thus a corresponding change in the synchronization signal. In this approach, the rendering frame rate and the encoding frequency may be “synchronized” in a manner consistent with the capacities of the server, the network, and the client device, resulting in generation, encoding, transmission, decoding, and presentation of a stream of frames that mitigates missed encoding of frames while providing acceptable latency.

Abstract: A processor supports secure memory access in a virtualized computing environment by employing requestor identifiers at bus devices (such as a graphics processing unit) to identify the virtual machine associated with each memory access request. The virtualized computing environment uses the requestor identifiers to control access to different regions of system memory, ensuring that each VM accesses only those regions of memory that the VM is allowed to access. The virtualized computing environment thereby supports efficient memory access by the bus devices while ensuring that the different regions of memory are protected from unauthorized access.

Abstract: A processing system identifies a subset of pages of memory allocated to a source guest virtual machine (VM) running at a first graphics processing unit (GPU) that were modified by the source guest VM and transferring only the subset to a destination guest VM running at a second GPU when performing a live migration from the source guest VM to the destination guest VM. The first GPU maintains a page table of system memory addresses or frame buffer addresses allocated to and accessed by the source guest VM during a session, including an indication of whether the data was modified. Based on the page table information, the processing system identifies and transfers only the modified pages from the source guest VM to the destination guest VM, thereby reducing the time and bandwidth used for migration.

Abstract: The present disclosure relates to techniques for allocating performance counters to virtual functions in response to a request from a respective one of the virtual functions. In response to receiving a request from a respective one of the virtual functions for a performance counter, a security processor is configured to allocate, via a controller, a register associated with a processor to the virtual function, such that the register is configured to implement the performance counter.

Abstract: The present disclosure relates to implementing a system for facilitating the migration of virtual machines and corresponding virtual functions from a source host machine to a destination host machine. A source computing device is configured to execute a plurality of virtual machines such that, each of the plurality of virtual machines is associated with at least one virtual function. In response to receiving a migration request, the source computing device is configured to save a state associated with a preempted virtual function for transfer to a destination computing device. The state associated with the preempted virtual function is a subset of a plurality of states associated with the plurality of virtual machines.

Abstract: An apparatus includes a graphics processing unit (GPU) and a frame buffer. The frame buffer is coupled to the GPU. Based upon initialization of a virtual function, a plurality of pages are mapped into a virtual frame buffer. The plurality of pages are mapped into the virtual frame buffer by using a graphics input/output memory management unit (GIOMMU) and an associated page table.

Abstract: A processing system identifies a subset of pages of memory allocated to a source guest virtual machine (VM) running at a first graphics processing unit (GPU) that were modified by the source guest VM and transferring only the subset to a destination guest VM running at a second GPU when performing a live migration from the source guest VM to the destination guest VM. The first GPU maintains a page table of system memory addresses or frame buffer addresses allocated to and accessed by the source guest VM during a session, including an indication of whether the data was modified. Based on the page table information, the processing system identifies and transfers only the modified pages from the source guest VM to the destination guest VM, thereby reducing the time and bandwidth used for migration.

Abstract: A system has a processor including a plurality of processor cores, a memory controller, and an input-output memory management unit. The plurality of processor cores implements a plurality of virtual machines. The system further has a device in communication with the input-output memory management unit, the device including a bus controller, a device memory controller, an encryption module, a device memory, and a computational resource. The device is to implement a plurality of virtual functions. The device provides a device memory access request from a virtual function to the device memory controller. The virtual function is associated with a virtual function identifier. The device is to determine an encryption key associated with the virtual function, decrypt information stored at the device memory using the encryption key, and provide the decrypted information in a processor memory access request to the processor.

Abstract: A processor supports secure memory access in a virtualized computing environment by employing requestor identifiers at bus devices (such as a graphics processing unit) to identify the virtual machine associated with each memory access request. The virtualized computing environment uses the requestor identifiers to control access to different regions of system memory, ensuring that each VM accesses only those regions of memory that the VM is allowed to access. The virtualized computing environment thereby supports efficient memory access by the bus devices while ensuring that the different regions of memory are protected from unauthorized access.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.

Abstract: Systems, apparatuses, and methods for accessing and managing memories are disclosed herein. In one embodiment, a system includes at least first and second processors and first and second memories. The first processor maintains a request log with entries identifying requests that have been made to pages stored in the second memory. The first processor generates an indication for the second processor to process the request log when the number of entries in the request log reaches a programmable threshold. The second processor dynamically adjusts the programmable threshold based on one or more first conditions. The second processor also processes the request log responsive to detecting the indication. Additionally, the second processor determines whether to migrate pages from the second memory to the first memory based on one or more second conditions.

Abstract: A request is sent from a new virtual function (VF) to a physical function for requesting the initialization of the new VF. The controlling physical function and the new VF establish a two-way communication channel that to start and end the VF's exclusive accesses to registers in a configuration space. The physical function uses a timing control to monitor that exclusive register access by the new VF is completed within a predetermined time period. The new VF is only granted a predetermined time period of exclusive access to complete its initialization process. If the exclusive access period is timed out, the controlling physical function can terminate the VF to prevent GPU stalls.

Abstract: A method and apparatus provides for the accommodation of display migration among a plurality of physical displays. In one example, the method and apparatus detects a display migration condition from at least a second physical display to a first physical display. The method and apparatus then controls compositing of a plurality of desktop surfaces so as enable access of each one of the plurality of desktop surfaces on the first physical display. The plurality of desktop surfaces include at least a desktop surface associated with the second physical display. The desktop surface is the content in a piece of memory in a frame buffer, which represents all the display content presented on the associated physical display. In one example, the plurality of desktop surfaces may be composited into at least one three-dimensional display object. The three-dimensional display object includes but is not limited to a revolving door object or other three-dimensional shape or object (e.g., a cube object).

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: A circuit monitors and resets a co-processor. The circuit includes a hang detector module for detecting a hang in co-processor. The circuit also includes a selective processor reset module for resetting the co-processor without resetting a processor in response to detecting a hang in the co-processor.

Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.

Abstract: An apparatus includes a plurality of image processing circuits. Each image processing circuit generates an image frame corresponding to a single large surface. The first image processing circuit provides a portion of the generated image frame for a first display or plurality of displays and provides a remaining portion of the image frame to the remaining image processing circuits. The next image processing circuits provides the remaining portion of the image frame for the next plurality of displays.

Abstract: A method and apparatus provides for the accommodation of display migration among a plurality of physical displays. In one example, the method and apparatus detects a display migration condition from at least a second physical display to a first physical display. The method and apparatus then controls compositing of a plurality of desktop surfaces so as enable access of each one of the plurality of desktop surfaces on the first physical display. The plurality of desktop surfaces include at least a desktop surface associated with the second physical display. The desktop surface is the content in a piece of memory in a frame buffer, which represents all the display content presented on the associated physical display. In one example, the plurality of desktop surfaces may be composited into at least one three-dimensional display object. The three-dimensional display object includes but is not limited to a revolving door object or other three-dimensional shape or object (e.g., a cube object).

Abstract: An apparatus includes a chrominance and luminance module. The chrominance and luminance module obtains display characteristics of each of a plurality of displays. The chrominance and luminance module selectively adjusts, on a per display basis, chrominance and luminance for each of the displays based on the display characteristics. In one example, the displays collectively display a single large surface.