Abstract: A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.

Abstract: A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.

Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.

Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.

Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.

Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.

Abstract: A method of manufacturing a semiconductor package includes providing a metallic leadframe having a plurality of cantilever leads and a mounting area for mounting a die, and disposing one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. The method further includes mounting the die in the mounting area and electrically connecting the die to the cantilever leads, and then encapsulating at least a portion of the die, the leadframe, and the supports with an encapsulant.

Abstract: A method of manufacturing a semiconductor package includes providing a metallic leadframe having a plurality of cantilever leads and a mounting area for mounting a die, and disposing one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. The method further includes mounting the die in the mounting area and electrically connecting the die to the cantilever leads, and then encapsulating at least a portion of the die, the leadframe, and the supports with an encapsulant.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent lands have their facing parallel perimeter portions oriented in parallel, defining a centerline. The land perimeters have flanges remote from the surface, each flange shaped by an outline. For adjacent lands, the flanges (207b, 218, 219) of the parallel perimeter portions have asymmetrical outlines relative to the centerline and are in concord so that alternately the flange of one land diminishes its outline where the flange of the adjacent land protrudes its outline. This coordinated variation shapes the space between the adjacent flanges in a meander-like mode. Adhesive plastic material is anchored in the space to hinder a land shift along the parallel perimeter portions.

Abstract: A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent lands have their facing parallel perimeter portions oriented in parallel, defining a centerline. The land perimeters have flanges remote from the surface, each flange shaped by an outline. For adjacent lands, the flanges (207b, 218, 219) of the parallel perimeter portions have asymmetrical outlines relative to the centerline and are in concord so that alternately the flange of one land diminishes its outline where the flange of the adjacent land protrudes its outline. This coordinated variation shapes the space between the adjacent flanges in a meander-like mode. Adhesive plastic material is anchored in the space to hinder a land shift along the parallel perimeter portions.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: Semiconductor dies and methods to mold lock a semiconductor die are disclosed. A disclosed example semiconductor die includes a top surface, a bottom surface, and a plurality of sides joining the top surface and the bottom surface. At least one of the sides includes an interference structure to mold lock the die in a package.