Patents by Inventor Jeffrey GEMAR
Jeffrey GEMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359373Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Engin Ipek, Hamza Omar, Bohuslav Rychlik, Saumya Ranjan Kuanr, Behnam Dashtipour, Michael Hawjing Lo, Jeffrey Gemar, Matthew Severson, George Patsilaras, Andrew Edmund Turner
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Patent number: 11636057Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.Type: GrantFiled: July 30, 2021Date of Patent: April 25, 2023Assignee: QUALCOMM IncorporatedInventors: Engin Ipek, Bohuslav Rychlik, George Patsilaras, Prajakt Kulkarni, Can Hankendi, Fahad Ali, Jeffrey Gemar, Matthew Severson
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Publication number: 20230031310Abstract: The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one “1” data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one “1” data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one “1” data values while reducing the number of zero “0” values, if reducing the number of zero values reduces energy consumption.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: ENGIN IPEK, Bohuslav RYCHLIK, George PATSILARAS, Prajakt KULKARNI, Can HANKENDI, Fahad ALI, Jeffrey GEMAR, Matthew SEVERSON
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Patent number: 11435804Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.Type: GrantFiled: February 13, 2020Date of Patent: September 6, 2022Assignee: QUALCOMM IncorporatedInventors: Jeffrey Gemar, Ambudhar Tripathi, Philippe Martin
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Publication number: 20210255689Abstract: In some aspects, the present disclosure provides a method for power management. The method includes receiving, by a power management unit (PMU), signaling indicative of a first plurality of latency durations from a first plurality of clients, each of the first plurality of latency durations corresponding to one of the first plurality of clients, wherein each of the first plurality of clients is configured to utilize a first shared resource for communication of data. In certain aspects, the method also includes selecting, by the PMU, a first latency duration from the first plurality of latency durations based on a determination that the first latency duration is the shortest latency duration of the first plurality of latency durations, and transitioning, by the PMU, the first shared resource from an active state to the first idle state.Type: ApplicationFiled: February 13, 2020Publication date: August 19, 2021Inventors: Jeffrey GEMAR, Ambudhar TRIPATHI, Philippe MARTIN
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Patent number: 11029745Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.Type: GrantFiled: November 8, 2018Date of Patent: June 8, 2021Assignee: QUALCOMM IncorporatedInventors: Kyle Ernewein, Jason Edward Podaima, Francisco Perez, John Daniels, Alex Miler, Jeffrey Gemar, Rexford Alan Hill, Haoping Xu
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Patent number: 10915157Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.Type: GrantFiled: February 14, 2019Date of Patent: February 9, 2021Assignee: QUALCOMM IncorporatedInventors: Dipti Ranjan Pal, Jeffrey Gemar, Abinash Roy
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Patent number: 10761774Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: GrantFiled: April 3, 2018Date of Patent: September 1, 2020Assignee: Qualcomm IncorporatedInventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Michael Hawjing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Publication number: 20200264682Abstract: In certain aspects, an apparatus includes a first power chain, a second power chain, and an enable circuit having an output coupled to an input of the first power chain. The apparatus also includes a multiplexer having a first input coupled to an output of the first power chain, a second input coupled to the output of the enable circuit, and an output coupled to an input of the second power chain, wherein the multiplexer is configured to receive a select signal, and couple the first input or the second input to the output of the multiplexer based on the select signal.Type: ApplicationFiled: February 14, 2019Publication date: August 20, 2020Inventors: Dipti Ranjan PAL, Jeffrey GEMAR, Abinash ROY
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Publication number: 20200073470Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.Type: ApplicationFiled: November 8, 2018Publication date: March 5, 2020Inventors: KYLE ERNEWEIN, JASON EDWARD PODAIMA, FRANCISCO PEREZ, JOHN DANIELS, ALEX MILER, JEFFREY GEMAR, REXFORD ALAN HILL, HAOPING XU
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Publication number: 20180225066Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Inventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Michael Hawjing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Patent number: 9965220Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: GrantFiled: February 5, 2016Date of Patent: May 8, 2018Assignee: QUALCOMM IncorporatedInventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Haw-Jing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Patent number: 9817470Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.Type: GrantFiled: February 24, 2016Date of Patent: November 14, 2017Assignee: QUALCOMM IncorporatedInventors: Suresh Sugumar, Jeffrey Gemar, Ali Taha, Amy Derbyshire, Tao Xue, Mohammad Tamjidi, Rajat Mittal
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Patent number: 9673787Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.Type: GrantFiled: September 22, 2015Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Lipeng Cao, Jeffrey Gemar, Ramaprasath Vilangudipitchai
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Patent number: 9612636Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.Type: GrantFiled: September 25, 2014Date of Patent: April 4, 2017Assignee: QUALCOMM IncorporatedInventors: Matthew Levi Severson, Shih-Hsin Jason Hu, Dipti Ranjan Pal, Madan Krishnappa, Jeffrey Gemar, Noman Ahmed, Mohammad Tamjidi, Mark Kempfert
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Publication number: 20170085253Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.Type: ApplicationFiled: September 22, 2015Publication date: March 23, 2017Inventors: Lipeng CAO, Jeffrey GEMAR, Ramaprasath VILANGUDIPITCHAI
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Publication number: 20160246362Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.Type: ApplicationFiled: February 24, 2016Publication date: August 25, 2016Inventors: Suresh SUGUMAR, Jeffrey GEMAR, Ali TAHA, Amy DERBYSHIRE, Tao XUE, Mohammad TAMJIDI, Rajat MITTAL
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Publication number: 20160091939Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.Type: ApplicationFiled: September 25, 2014Publication date: March 31, 2016Inventors: Matthew Levi SEVERSON, Shih-Hsin Jason HU, Dipti Ranjan PAL, Madan KRISHNAPPA, Jeffrey GEMAR, Noman AHMED, Mohammad TAMJIDI, Mark KEMPFERT