Abstract: A Doherty amplifier system (10) is disclosed having a carrier amplifier (12) with a carrier drain bias input (14), and a peak amplifier (24) having a peak drain bias input (26), and a peak gate bias input (28). Also included is a programmable bias controller (40) having a data interface configured to receive peak-to-average power ratio (PAPR) data associated with a basestation. The programmable bias controller (40) further includes a processor (46) coupled to the data interface and configured, in response to the PAPR data, to determine and apply bias levels to the carrier drain bias input (14), the peak drain bias input (26), and the peak gate bias input (28) to provide an amplifier efficiency between 30% and 78.5%.

Abstract: A load-modulated amplifier system is disclosed having a main amplifier with drain or collector voltage bias input, and an auxiliary amplifier having a static drain or collector voltage bias input. Also disclosed is a programmable voltage bias controller having a data interface configured to receive operating traffic level data symbol data associated with a basestation. The programmable bias controller further includes a processor coupled to the data interface and configured, in response to the traffic or symbol data, to determine and apply bias levels to the carrier drain or collector bias input and the auxiliary drain or collector bias input and to provide an amplifier efficiency theoretically between 60% and 78.5% over the low traffic operation zone ?9 dB to ?15 dB backed off from amplifier peak power.

Abstract: A radio frequency (RF) control circuit is provided. The RF control circuit includes power amplifier (PA) circuitry for amplifying an RF signal and control circuitry configured to improve linearity of the PA circuitry based on a PA signature(s) already available and utilized to perform digital pre-distortion (DPD) in the RF control circuit. In examples discussed herein, the control circuitry determines a performance deviation of the PA circuitry based on the PA signature and continuously adjusts a bias voltage(s) supplied to the PA circuitry until the performance deviation is reduced to a predetermined performance deviation threshold. By continuously monitoring the performance deviation based on the PA signature(s) and adjusting the bias voltage(s), the control circuitry can detect and correct an operation abnormality of the PA circuitry in a timely manner. As a result, it is possible to maintain linearity in the PA circuitry for enhanced PA performance.

Abstract: A radio frequency (RF) control circuit is provided. The RF control circuit includes power amplifier (PA) circuitry for amplifying an RF signal and control circuitry configured to improve linearity of the PA circuitry based on a PA signature(s) already available and utilized to perform digital pre-distortion (DPD) in the RF control circuit. In examples discussed herein, the control circuitry determines a performance deviation of the PA circuitry based on the PA signature and continuously adjusts a bias voltage(s) supplied to the PA circuitry until the performance deviation is reduced to a predetermined performance deviation threshold. By continuously monitoring the performance deviation based on the PA signature(s) and adjusting the bias voltage(s), the control circuitry can detect and correct an operation abnormality of the PA circuitry in a timely manner. As a result, it is possible to maintain linearity in the PA circuitry for enhanced PA performance.

Abstract: A circuit for protecting an electronic device including a differential nulling avalanche clamp circuit (200, 300) and method of using the circuit in an electronic system (100) to limit radio frequency overdrive. The electronic system (100) includes a surge clamp (130) coupled to dissipate an electrical surge effect of a first frequency from a noise sensitive node (140) and a ring wave clamp (120) coupled to dissipate an electrical surge effect of a second frequency from the noise sensitive node (140). The ring wave clamp circuit (200, 300) includes a first bipolar junction transistor (210, 310), a second bipolar junction transistor (220, 320) coupled to the first bipolar junction transistor (210, 310), and a resistive circuit (230, 330, 340) coupled to the first and second bipolar junction transistors (210, 220, 310, 320).