Patents by Inventor Jeffrey Gongxian Cheng
Jeffrey Gongxian Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230055695Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.Type: ApplicationFiled: October 7, 2022Publication date: February 23, 2023Inventors: Anirudh R. Acharya, Michael J. Mantor, Rex Eldon McCrary, Anthony Asaro, Jeffrey Gongxian Cheng, Mark Fowler
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Patent number: 11467870Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.Type: GrantFiled: July 24, 2020Date of Patent: October 11, 2022Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anirudh R. Acharya, Michael J. Mantor, Rex Eldon McCrary, Anthony Asaro, Jeffrey Gongxian Cheng, Mark Fowler
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Patent number: 11100604Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.Type: GrantFiled: January 31, 2019Date of Patent: August 24, 2021Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jeffrey Gongxian Cheng, Ahmed M. Abdelkhalek, Yinan Jiang, Xingsheng Wan, Anthony Asaro, David Martinez Nieto
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Publication number: 20210011760Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.Type: ApplicationFiled: July 24, 2020Publication date: January 14, 2021Inventors: Anirudh R. Acharya, Michael J. Mantor, Rex Eldon McCrary, Anthony Asaro, Jeffrey Gongxian Cheng, Mark Fowler
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Publication number: 20200250787Abstract: Systems, apparatuses, and methods for scheduling jobs for multiple frame-based applications are disclosed. A computing system executes a plurality of frame-based applications for generating pixels for display. The applications convey signals to a scheduler to notify the scheduler of various events within a given frame being rendered. The scheduler adjusts the priorities of applications based on the signals received from the applications. The scheduler attempts to adjust priorities of applications and schedule jobs from these applications so as to minimize the perceived latency of each application. When an application has enqueued the last job for the current frame, the scheduler raises the priority of the application to high. This results in the scheduler attempting to schedule all remaining jobs for the application back-to-back. Once all jobs of the application have been completed, the priority of the application is reduced, permitting jobs of other applications to be executed.Type: ApplicationFiled: January 31, 2019Publication date: August 6, 2020Inventors: Jeffrey Gongxian Cheng, Ahmed M. Abdelkhalek, Yinan Jiang, Xingsheng Wan, Anthony Asaro, David Martinez Nieto
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Patent number: 10725822Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.Type: GrantFiled: July 31, 2018Date of Patent: July 28, 2020Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Anirudh R. Acharya, Michael J. Mantor, Rex Eldon McCrary, Anthony Asaro, Jeffrey Gongxian Cheng, Mark Fowler
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Publication number: 20200042348Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.Type: ApplicationFiled: July 31, 2018Publication date: February 6, 2020Inventors: Anirudh R. Acharya, Michael J. Mantor, Rex Eldon McCrary, Anthony Asaro, Jeffrey Gongxian Cheng, Mark Fowler
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Patent number: 9176794Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.Type: GrantFiled: November 4, 2011Date of Patent: November 3, 2015Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Jeffrey Gongxian Cheng, Paul Blinzer, Mark Hummel, Leendert Peter Van Doorn
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Publication number: 20120147021Abstract: A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.Type: ApplicationFiled: November 4, 2011Publication date: June 14, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Jeffrey Gongxian CHENG, Paul BLINZER, Mark HUMMEL, Leendert Peter VAN DOORN
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Patent number: 7663635Abstract: A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics aperture relocation table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. Thus, unique addresses need not be generated for each VPU.Type: GrantFiled: May 27, 2005Date of Patent: February 16, 2010Assignee: ATI Technologies, Inc.Inventors: Philip J. Rogers, Jeffrey Gongxian Cheng, Dmitry Semiannikov, Raja Koduri
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Patent number: 7657897Abstract: The present application discloses a method for communicating between at least two different levels of software components. The method includes establishing a command set common to the at least two different levels of software components. Additionally, the method includes providing a command decoder operable by both of the at least two levels of software components, the command decoder configured to decode the command set. By providing a common command set between different levels of software components, such as a software driver and a BIOS, where the commands within the command table are interpreted and executed by an identical command decoder that interprets and executes the same command tables, this ensures that the same features or functions are implemented or executed in the same way across different levels of the software components. Accordingly, redundant implementation of the same functions by different software components is eliminated.Type: GrantFiled: May 4, 2005Date of Patent: February 2, 2010Assignee: ATI Technologies ULCInventors: Zheng Huang, Efim Neiman, Jae Chong, Velodymyr Stempen, Jeffrey Gongxian Cheng, Vladimir F. Giemborek, Andrej Zdravkovic
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Publication number: 20040153778Abstract: A system and method for configuring graphics processing communication among a graphics device, a chipset (a host bridge), and a data processor is shown and described. A graphics driver is used to configure graphics communication within an information handling system using existing information stored in system memory or installing and running a configuration routine to determine a method of graphics communication. A configuration routine applies tests to determine a mode of data transfer between the system and the graphics device. Test results associated with the configuration routine are stored and can be loaded upon subsequent system startups to configure communications between the system and the graphics device. A reliable mode for communicating between the graphics device and the information handling system is established to allow the graphics device to be used without requiring excessive interaction by a user.Type: ApplicationFiled: April 2, 2003Publication date: August 5, 2004Applicant: ATI Technologies, Inc.Inventor: Jeffrey Gongxian Cheng