Abstract: A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.

Abstract: A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a second gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second passgate.

Abstract: A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.

Abstract: A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage.

Abstract: A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.

Abstract: A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage.

Abstract: A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second pass-gate.

Abstract: A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line.

Abstract: Disclosed is a method for segmenting functionality of a hybrid built-in self test (BIST) architecture for embedded memory arrays into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Abstract: Disclosed in a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Abstract: Disclosed is a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction set. A block of higher-speed test logic is incorporated into each embedded memory array under test and locally processes BIST instructions received from the standalone BIST logic controller at a higher frequency. The higher-speed test logic includes a multiplier for increasing the frequency of the BIST instructions from the lower frequency to the higher frequency. The standalone BIST logic controller enables a plurality of higher-speed test logic structures in a plurality of embedded memory arrays.

Abstract: A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

Abstract: A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.

Abstract: A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: A method and circuit for a self timed DRAM. The circuit includes interlock circuits coupled to an extension of the DRAM. The extension does not store “real” data but mimics the operations of the DRAM. The interlock circuits, in conjunction with the extension monitor and control read and write timings of the DRAM and self adjust these timings via feedback. To properly track DRAM cell timings, the interlock circuits and extension use the same cell design and load conditions as the DRAM. The method includes: activating a wordline and reference wordline, interlocking the sense amplifiers, column select and write back functions of the primary DRAM array by monitoring the identical reference cells and the state of the bitline in the extension DRAM array.

Abstract: A method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.

Abstract: A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt.

Abstract: A programmable data generator for generating input test data to be applied to a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.

Abstract: Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in.