Abstract: A multi-board mid-plane includes a disk backplane board (DBB) having a front side and a rear side. Venting holes are provided within the DBB extending between the front side of the DBB and the rear side of the DBB. The multi-board mid-plane also includes a controller backplane board (CBB) having a front side and a rear side. The front side of the CBB includes venting holes provided within the CBB extending between the front side of the CBB and the rear side of the CBB. A top fabric plane board (TFPB) and a bottom fabric plane board (BFPB) are provided for connecting the DBB with the CBB. A combination of the DBB and the CBB has a venting ratio that is equal to a lower of the venting ratio of the DBB and the venting ratio of the CBB.

Abstract: A multi-board mid-plane includes a disk backplane board (DBB) having a front side and a rear side. Venting holes are provided within the DBB extending between the front side of the DBB and the rear side of the DBB. The multi-board mid-plane also includes a controller backplane board (CBB) having a front side and a rear side. The front side of the CBB includes venting holes provided within the CBB extending between the front side of the CBB and the rear side of the CBB. A top fabric plane board (TFPB) and a bottom fabric plane board (BFPB) are provided for connecting the DBB with the CBB. A combination of the DBB and the CBB has a venting ratio that is equal to a lower of the venting ratio of the DBB and the venting ratio of the CBB.

Abstract: An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80).

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.