Patents by Inventor Jeffrey H. Oppold
Jeffrey H. Oppold has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8196088Abstract: A method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-based NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.Type: GrantFiled: December 3, 2007Date of Patent: June 5, 2012Assignee: International Business Machines CorporationInventor: Jeffrey H. Oppold
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Patent number: 7870525Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.Type: GrantFiled: May 16, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson
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Publication number: 20100174503Abstract: An apparatus for directly measuring performance offset of NFET transistors with respect to PFET transistors in CMOS device processing includes a ring oscillator whose frequency is used to measure random across chip variations, as well as correlated across chip variations; a balanced inverter having a input driven by the ring oscillator, wherein the balanced inverter is designed to be formed such that a current drive capability of one or more NFET devices of the inverter is substantially equal to a current drive capability of one or more PFET devices of the inverter at a given operating temperature; and a capacitor coupled to an output of the inverter, with a voltage across the capacitor indicative of whether a skew exists between NFET device performance and PFET device performance.Type: ApplicationFiled: January 7, 2009Publication date: July 8, 2010Applicant: International Business Machines CorporationInventors: Bruce Balch, Anthony Wayne Fazekas, Mark C.H. Lamorey, Jeffrey H. Oppold, Joseph James Oler, JR., Chirstopher Daniel Parkinson
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Patent number: 7716616Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.Type: GrantFiled: October 31, 2007Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson
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Publication number: 20090140245Abstract: A design structure of a method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.Type: ApplicationFiled: May 28, 2008Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Jeffrey H. Oppold
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Publication number: 20090144024Abstract: A method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-based NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.Type: ApplicationFiled: December 3, 2007Publication date: June 4, 2009Inventor: Jeffrey H. Oppold
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Publication number: 20080216036Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.Type: ApplicationFiled: May 16, 2008Publication date: September 4, 2008Inventors: Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson
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Patent number: 7401307Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.Type: GrantFiled: November 3, 2004Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Eric A. Foreman, Peter A. Habitz, David J. Hathaway, Jerry D. Hayes, Jeffrey H. Oppold, Anthony D. Polson
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Patent number: 7117428Abstract: A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.Type: GrantFiled: November 8, 2005Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Jeffrey H Oppold, Michael R Ouellette, Larry Wissell
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Patent number: 6917221Abstract: An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.Type: GrantFiled: April 28, 2003Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Stephen V. Kosonocky, Randy W. Mann, Jeffrey H. Oppold
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Publication number: 20040251496Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).Type: ApplicationFiled: June 11, 2003Publication date: December 16, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey S. Brown, Chung H. Lam, Randy W. Mann, Jeffrey H. Oppold
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Publication number: 20040216015Abstract: An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.Type: ApplicationFiled: April 28, 2003Publication date: October 28, 2004Applicant: International Business Machines CorporationInventors: Kerry Bernstein, Stephen V. Kosonocky, Randy W Mann, Jeffrey H. Oppold
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Patent number: 6778449Abstract: A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.Type: GrantFiled: July 1, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Jeffrey S. Brown, Randy W. Mann, Jeffrey H. Oppold
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Patent number: 6420746Abstract: A semiconductor integrated circuit memory cell, including at least three transistors and a capacitor to form a DRAM. The memory cell is fabricated on a semiconductor substrate including impurity regions, and using two semiconductor films, with dielectric films between the semiconductor films. The capacitor contains two electrodes. A substrate impurity region forms one of the electrodes; the other electrode is a semiconductor film which connects the gate of one device to an impurity region of another. The method for manufacturing the above-described integrated circuit, which may be used for the manufacture of similar circuits, is also disclosed.Type: GrantFiled: October 29, 1998Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: John A. Bracchitta, Randy W. Mann, Jeffrey H. Oppold