Abstract: A sensor system is adapted for use with an article of footwear and includes an insert member including a first layer and a second layer, a port connected to the insert and configured for communication with an electronic module, a plurality of force and/or pressure sensors on the insert member, and a plurality of leads connecting the sensors to the port.

Abstract: A reflective wire grid polarizer (WGP) can include an array of wires 12 on a face of a substrate 11, with channels 15 between adjacent wires 12. The wires 12 can have certain characteristics for WGP performance, such as index of refraction, alternating high/low index continuous thin films, thickness of layer(s), duty cycle, reflective rib shape, a curved side of transparent ribs 21 or 32, aspect ratio, or combinations thereof.

Abstract: A reflective wire grid polarizer (WGP) can include an array of wires 12 on a face of a substrate 11, with channels 15 between adjacent wires 12. The wires 12 can have certain characteristics for WGP performance, such as index of refraction, alternating high/low index continuous thin films, thickness of layer(s), duty cycle, reflective rib shape, a curved side of transparent ribs 21 or 32, aspect ratio, or combinations thereof.

Abstract: A reflective wire grid polarizer (WGP) can include an array of wires 12 on a face of a substrate 11, with channels 15 between adjacent wires 12. The wires 12 can have certain characteristics for WGP performance, such as index of refraction, alternating high/low index continuous thin films, thickness of layer(s), duty cycle, reflective rib shape, a curved side of transparent ribs 21 or 32, aspect ratio, or combinations thereof.

Abstract: A semiconductor apparatus includes a metal substrate, a doped silicon layer on the metal substrate, a semiconductor layer overlying the doped silicon layer, and semiconductor structures having one or more p-n junctions at least partially within the semiconductor layer formed by using layering, patterning, and doping steps. In an embodiment, the doped silicon layer comprises a heavily doped silicon layer. In another embodiment, the doped silicon region has a thickness that is less than a thickness of a cleavable region formed by ion implantation. In a specific embodiment, the thickness of the cleavable region is about 1-2 um. In another embodiment, the semiconductor layer has a thickness of approximately 10 um. In another embodiment, the semiconductor structures includes a vertical power MOSFET with the metal substrate configured to be a drain terminal contact region.

Abstract: Processes used to transfer semiconductor structures from an initial substrate to a base substrate include bonding the initial substrate with a silicon dioxide layer to a doped silicon structure weakened sufficiently by hydrogen implantation for cleaving. After cleaving, a doped silicon layer remains, burying the silicon dioxide layer between the doped silicon layer and the initial substrate. Semiconductor structures are formed within/on an epitaxial layer disposed on the doped silicon layer forming an intermediate semiconductor structure. A process handle is temporarily bonded to the semiconductor structures for support. The initial substrate is thinned and removed by a mechanical thinning process followed by chemical etching using the buried silicon dioxide layer as an etch stop. The silicon dioxide layer is chemically removed from the doped silicon layer. A base substrate is formed on the doped silicon layer. The process handle is removed leaving the semiconductor structures disposed on the base substrate.